This paper proposes an Ambient-Adaptive Voltage Scaling (AAVS) driver for SPAD arrays that maintains quasi-linear photon detection across a wide range of illumination levels. The proposed system integrates an Adaptive Feedback-Controlled (AFC) V${}_{\mathbf {EX}}$modulator that continuously senses photon flux to regulate the excess bias voltage (V${}_{\mathbf {EX}}$) relative to the actual breakdown voltage (V${}_{\mathbf {BD}}$), coupled with a hybrid boost converter featuring adaptive V${}_{\mathbf {EX}}$calibration to generate 27.1–27.6V with sub-millivolt ripple. Measurement results demonstrate a 131 dB dynamic range ($10^{10}$–$10^{17}$photons/cm${}^{2}\cdot $s), 92.3% peak efficiency, and robust scalability supporting 128-SPAD arrays. The AAVS architecture enhances sensitivity under low-light conditions while effectively preventing saturation in high-light scenarios.

In recent years, the complexity of neural network (NN) models has increase continuously, resulting in a substantial increase in multiply-accumulate (MAC) operations. Therefore, the need for area- and power-efficient DRAM compute-in-memory (CIM) designs has become a pressing issue. The proposed CIM design uses the reverse rotating charge sharing (RRCS) technique to save 79% of silicon area compared to conventional designs. In addition, the use of the proposed low-threshold prediction technique can reduce analog-to-digital converter (ADC) calculations by 25% and ADC power consumption by 17%. Energy efficiency and area reduction are 10x and 1900x, respectively, higher than previous CIM designs.

The conventional capacitor-switch-inductor (C-S-L) topology suffers from significant conduction loss and sluggish transient response due to the series power switches conduction inherent in its structure. To address these limitations, the proposed rotated hybrid converter adopts a rotated mechanism and parallel conduction within the capacitor-two-switch-inductor (C-2S-L) topology, effectively reducing current stress on components. This approach enhances efficiency while mitigating the effects of parasitic inductance from bond wires. During transient conditions, all C-2S-L stages can be simultaneously activated, enabling a near-full duty cycle (D). Experimental results demonstrate a minimal undershoot of 96 mV and a fast settling time of 0.92 μs during a load step from 2 A to 10 A within 20 ns. Additionally, the converter integrates phase shedding, dynamically adjusting the number of active phases according to load conditions to optimize efficiency across a broad load range. Therefore, the proposed C-2S-L topology achieves a peak efficiency of 92.6% at an output voltage (VOUT) of 1.2 V and a load current (ILOAD) of 3A.

This paper proposes a flying-capacitor sharing dynamic four-path (FCSD-4P) hybrid converter, designed to achieve a duty cycle (D) ranging from 0% to 100%, addressing the conventional limitation of D2. In a 6V to 1.8V conversion, the converter achieves a peak efficiency of 94.2%.

This paper proposes a two-step down converter based on Pseudo 4-Phase Mutual Operation (P4MO) that uses inductors and coupled inductors to regulate output voltage (VOUT). By doubling the inductor current slew rate, the design reduces the intermediate capacitor (CINT) at VINTby nearly 50%. Additionally, conduction losses in the dual-output triple step-down (DOTS) input stage are reduced by approximately 30%. Moreover, a delayed feedback PWM technique further reduces the VINTripple by about 20%. An integrated soft turn-off circuit minimizes voltage variations at VOUTto less than 2 mV during phase shedding. Experimental results validate the design’s performance, showing a peak efficiency of 93.1%, undershoot of 106 mV with a recovery time of 1.9 μs for a load step transition from 1 A to 20 A, and a transient performance of 5.58 mV/A.

In this paper, the proposed multi-phase (MP) bidirectional dual Gallium-Nitride (GaN) controlled rectifier (GCR) uses dual GCR with the pre-charge technique to reduce third quadrant operation by minimizing dead time to 0.12ns and 0.13ns, and lowering the negative VDS to −0.6V and −0.8V in buck and boost operation, respectively. This work is the first research for monolithic bidirectional energy transfer with a two-switch-only topology. With the help of MP-accelerated current control and the GCR dynamic ramp generator, the voltage variation on the high-voltage (HV) side and low-voltage (LV) side can be reduced to less than 50mV and to 40mV, respectively, during buck and boost operation transitions. Moreover, the recovery time is effectively reduced and current balance between the four phases can be achieved within 7 cycles (=350ns). The peak efficiency is as high as 95.5% and 94.2% in buck and boost operation, respectively.

This paper proposes an isolated gate driver that incorporates an enhanced common-mode transient immunity (CMTI) technique to effectively suppress common-mode transient (CMT) noise. Additionally, the approach leverages the CMT noise to enable on-the-fly deadtime (DT) control at the transmitter. Experimental results demonstrate the DT jitter compensation circuit reduces high-frequency carrier (500 MHz) jitter by 10.6%, the efficiency is improved by 11.5%, and the CMTI is improved from 184 kV/μs to 208 kV/μs.

This paper proposes a two-phase hybrid buck-boost converter, which meets the criteria of USB PD 3.1, with an auxiliary inductor LAUX to achieve soft switching by the zero voltage switching (ZVS) technique at light loads. Besides, two interleaving phases can reduce the inductor current to half of that conventional design. Benefiting from a coupled inductor with a negative mutual inductance (M$_{\mathrm {L(AC)}}$becomes small to achieve low output voltage ripple due to large equivalent inductance Leq in a steady state. Based on the loading current, the phase shedding can change the number of driving phases for high efficiency. Moreover, a transient enhancement circuit is proposed to speed up transient response time. The proposed circuit achieves the maximum inductor current ripple reduction of 9.09% and the maximum P$_{\mathrm {AC\_loss}}$reduction of 17.36% at D=0.5. Experimental results show 96.1% peak efficiency. In the case of the load step 0.5A to 5A, the recovery time and undershoot are reduced to$10.7\mu $s and 133mV, respectively, and in the case of the load step 5A to 0.5A, the recovery time and overshoot are reduced to$9.4\mu $s and 147mV, respectively.

This paper proposes a series-parallel bond wire auxiliary fully integrated step-up switched-capacitor (SC) converter with conversion ratio expansion to improve the trade-off between power loss and output voltage ripple. The series-parallel switching strategy reduces the burden of delivering charges in a 1:2 SC and also extends the output-input voltage ratio range. In addition, the$\text{L}_{\mathbf {BOND}}$mismatch calibration (LMC) technique can eliminate the mismatch between bond wires. Moreover, the binary flying capacitor scaling technique automatically optimizes the capacitance of the flying capacitor to ensure a well-controlled output voltage ripple over a wide load range. With only 250pF total capacitors in use, the experimental results show a well-controlled ripple under 23.86mV and efficiency greater than 75% over a load range of 1mA to 20mA. Furthermore, this technique has a smooth efficiency profile within an input voltage level of 0.63V to 0.9V with a peak efficiency of 85% and an output voltage of 0.95V.

this paper proposes a new dual-mode low-dropout linear regulator without external capacitors, which includes three error amplifiers, an offset voltage generator, a mode decision circuit, and a pre-biasing load transient enhancement circuit. The chip uses a 28nm CMOS process to verify the advantages brought by the architecture of this work. The measurement results show that the output voltage has a negligible undershoot and overshoot (both less than 5mV) during mode transition. In load transient response, due to the use of pre-charge technique, the output voltage undershoot and overshoot are reduced by 45.2% and 36%, respectively. Finally, this architecture achieves FoM to be close to 1fs.

the proposed distributive digital low dropout (DLDO) regulator utilizes the triple binary successive approximation recursive (SAR) control algorithm for fast transient response. In addition, the body voltage control (BVC) can be used to expand the least significant bit (LSB) to enhance the accuracy. In case of load transients, the BVC can further increase or decrease the driving capability for fast transient response. Experimental results show that the voltage droop can be less than 72 mV at $F_{\text{CLK}}=100 \text{MHz}$, accomplishing a fast settling time of 3.6 ns. Burst cells and lossless cells can maintain overshoot below 68 mV with the settling time of 11.2 ns. The BVC technique reduces output voltage ripple to less than 0.4 mV in the steady-state.

Ultra-low quiescent current ($I_{Q}$) low-dropout regulator is the only solution for compact size Internet of Things (IoT) electronic devices. This paper presents an ultra-low$I_{Q}$low dropout regulator, including low$I_{Q}$error amplifier (EA) compensated by the adaptive current control (ACC), low leakage feedback network, low$I_{Q}$current comparator, analog transient enhancement (ATE), and digital transient enhancement (DTE). The chip was fabricated in a standard$0.5~\mu \text{m}$CMOS process. Measurement results show the current peak efficiency of the LDO is as high as 99.99%. Besides, owing to ATE and DTE circuits, when the load current changes from 1mA to 50mA with a 10 ns edge time, the measured undershoot and overshoot voltages are 75 mV and 50 mV, respectively, with the recovery time ($T_{R}$) of 60 ns and 80 ns, respectively, where the best 0.003 ps FoM is achieved.

The series stacked (SS) FinFET structure is used in digital low dropout (DLDO) regulators to withstand high input voltages and implement dynamic voltage scaling (DVS) technique with minimum energy point (MEP) technique. Through an additional delay consideration in MEP, both energy reduction and performance of the Cortex M0 processor can achieve 34.5pJ/cycle at 0.5V. Maximum energy reduction is about 37.5% and the supplying voltage varies from 0.4V to 0.775V with a search time of 2.5μs for each voltage step. The proposed SS-DLDO has fast settling time and low output voltage ripple of 1.5μs and 5mV, respectively.

This paper proposed MicroLED virtual pixel array design and driver. The proposed virtual pixel array effectively increases the pixels per inch (PPI) while having a relatively low ghosting. The push-pull supply buffer in the proposed driver is compensated by the dynamic Miller compensation (DMC) technique to reduce the ghosting by 50%-73%. Four times screen resolution can be obtained compared to conventional designs. 95% high efficiency microLED driver has the lowest 45μW power consumption.

This paper presents a fast transient low-dropout regulator (LDO) with bulk modulation technique and dynamic transient boost circuit (TBC) for system-on-chip (SoC) applications. The conventional bulk modulation and dynamic biasing techniques failed to obtain low quiescent current and better stability at no-load conditions. The proposed bulk modulation technique implemented by using only one error amplifier with two different gain stages to achieve the small quiescent current and to obtain good regulation with better driving capability. The proposed TBC combines the dynamic biasing and output compensation techniques to enhance the transient response of LDO drastically. The proposed design is simulated in the 40nm LVT CMOS process shows that the LDO delivers 1V output voltage and consumes 15μA of quiescent current with the supply voltage of 1.1V. When the load current changes from 100nA to 10mA with a large slew rate of 200ps, undershoot and settling time are 450mV and 8ns respectively. Compared to LDO without TBC, the proposed LDO offers good stability, better driving capability, ~10× less undershoot and ~10× fast settling time.

This paper proposes an active clamp flyback (ACF) converter with GaN devices. Compared to Si FETs, when the main GaN FET is at full zero voltage switching (FZVS), maximum switching loss reduction can be achieved. Thus, the use of dynamic resonant period control (DRPC) technique to achieve fast ZVS can reduce 87% of the transformer leakage inductance energy loss on the active resonant circuit (ARC). When the load changes, the DRPC technique dynamically adjusts the auxiliary switch on-time to prevent large voltage stress on the primary side components. At full load, the leakage energy loss can be reduced, thereby transferring more energy to the secondary side with an efficiency of up to 94%.

This paper presents a LDO-controlled current sensor for accelerating constant on-time (COT) switching regulators (SWRs) for high efficiency envelope tracking power modulators (ETSMs) for RF power amplifiers (RF PAs). The proposed LDO-controlled current sensor controls the feedback loop of the SWR, rather than the traditional current sensing technique, in the case of fast envelope tracking. The LDO regulator behaves as the master to rapidly trigger the SWR as a slave energy provider to rapidly deliver the average energy to the RF PA for high efficiency. The experimental results show that the test chip fabricated in 0.18μm CMOS process can accurately track the RF envelope signal, and the peak efficiency is 86.7% when the power is 0.95W.

It is crucial in near field communication (NFC) controllers for power source transferred from mutual induction of coils when the devices are battery-off. NFC devices can be operated at the condition of low battery or even battery-off due to the requirement of payment any time. Thus, the proposed wireless power transfer (WPT) power supply can have high efficiency due to the remove of reverse leakage current by the digital reverse current self-calibration (DRCS). NFC standards including A, B, and F can be continuously supplied by the WPT supply system. The WPT power supply with the DRCS technique was fabricated in 0.25μm CMOS process can rectify AC source from induction of magnetic field to unregulated DC voltage source and to supply power the NFC controller through low dropout regulator (LDR). Moreover, test chip achieves as high as 92% voltage conversion ratio and 89.4 % power conversion efficiency (PCE) due to reduction of unnecessary current loss.

The non-isolated buck topology for LED driver is proposed to reduce volume and cost without the need of large transformer. Besides, in the entire universal range of AC input voltage, the proposed self-adjusted feed-forward control (SAFFC) technique ensures small variation in the LED current. The auto-tracking off-time control (ATOTC) technique is also adopted to adjust the off time to guarantee the current accuracy is better than that of the peak current control (PCC) technique while and the efficiency is better than that of the hysteresis current control (HCC) technique. Test chip fabricated in VIS 0.5μm 700V ultra-high voltage (UHV) process demonstrates power factor higher than 0.97, averaged 95% high accuracy, and 95% high efficiency.

This paper proposed the adaptive knee voltage detection (KVD) technique to improve the output voltage accuracy of the primary side regulator. Owing to the insertion of the snubber circuit for reducing overshoot voltage, conventional KVD technique fails to get the output voltage information and thus to deteriorate the output voltage accuracy. Analysis of the snubber circuit and the resonance of the primary side can determine the band-pass filter in the proposed AKVD technique to get high accuracy output information without being affected by any kinds of resonances. Test chip designed in VIS 0.5μm BCD process demonstrates the accuracy of the output voltage higher than 99%. Besides, any abnormal detection won't happen and thus the output ripple can be kept low.

Implantable devices like artificial cardiac pacemakers are generally used to control irregular pulses of heart. For 10-year usage, high accuracy supply voltage is essential with the unavoidable aging of the power system to achieve near-natural beat rhythm. A Self-Calibration DC-DC Buck converter (SC-Buck) is proposed to achieve high output voltage accuracy by eliminating offset caused by mismatch of process, voltage and temperature (PVT). Furthermore, the discontinuity which affects transient performance in conventional offset cancellation is also overcome. Large area occupation, which is required to decrease mismatch in conventional operational amplifier, can be largely decreased according to Monte Carlo analysis. Without trimming process, the proposed SC-Buck technique achieves high accuracy for long-term usage (years) and low cost. The test chip fabricated in UMC 28nm CMOS process proves the output voltage accuracy of 97% since the mismatch of error amplifier can be suppressed from 122% to 1%.

This paper repots an optimum on-time (OOC) control with predicting correction technique (PCT) for ripple-based buck converter. The switching frequency (FSW) variation is analyzed with completely considering the parasitic resistances of the components and devices. The proposed converter achieved nearly constant switching frequency over a wide load range without extra clock controlled circuits and current sensing circuits. The parameters of the parasitic resistances almost cause no influence and no restriction on FSWperformance. Actually, only the input voltage is necessary to predict the optimum on-time, and this work benefits the decease on total pin numbers. The simulation results demonstrate 0.375% ΔFSW/FSWand 2kHz/A ΔFSW/ΔILOADover 1.5A load current change. Consequently, pseudo constant FSWwith known noise spectrum strongly benefits the solution of electromagnetic interference (EMI) issue for system-on-chip (SoC).

An increased damping resistor (IDR) replaces high-order loop filter to simply reduce the total harmonic distortion (THD) of Class-D audio amplifier. Besides, cross offset cancellation (COC) technique minimizes the system offset voltage to avoid dc current flows to the speaker in the bridge tied load (BTL) structure. Furthermore, variable switching frequency characteristic in self-oscillating modulation spreads the electro-magnetic interference (EMI) impact out on the output frequency spectrum. Experimental results demonstrate that the proposed Class-D amplifier can deliver 0.55W to the 8Ω load with a 3.3V supply voltage with 150-nm CMOS process. The power efficiency is over 90% and the output THD is smaller than 0.01% (80dB).

This paper presents a dual-level dual-phase pulse-width modulation (DLDP PWM) Class-D audio amplifier circuit which enhance amplifier linearity and reduce distortion. The proposed DLDP PWM Class-D audio amplifier includes two sets of non-overlapping triangular waves, each at its respectful offset levels. Each set of triangular waves is composed of two 180° out-of-phase triangular waves. The differential power stage consists of 8 power transistors, with voltage swings up to +/- 6V. Simulated results shows that the proposed DLDP PWM Class-D audio amplifier features an SNR up to 105 dB, and the THD is suppressed below 0.001 %, with the 3rd harmonic below -102 dBV.

This article presents methods and circuits for synthesizing test signals in the time/frequency domain. An arbitrary signal is first encoded using sigma–delta modulation in the digital amplitude-domain and converted to the time or frequency domain through a digital-to-time converter (DTC) or digital-to-frequency converter (DFC) operation realized in software. In hardware, the resulting bit-stream is inputted cyclically to a high-order phase-locked loop (PLL) behaving as a time-mode reconstruction filter in the appropriate domain (time or frequency). A high-speed prototype implementation consisting of a 4th order PLL built in 0.13 μm complementary metal oxide semiconductor (CMOS) process with an off-chip loop filter has been fabricated and used to generate signals at 4 GHz. The digital nature and portability of the phase/ frequency test signal generation process makes the proposed scheme compatible with the IEEE 1149.1 test bus standard and easily amenable to any testing environment: production, characterization, design-for-test (DFT), or built-in self-test (BIST).