The CydraTM 5 architecture adds unique support for overlapping successive iterations of a loop to a very long instruction word (VLIW) base. This architecture allows highly parallel loop execution for a much larger class of loops than can be vectorized, without requiring the unrolling of loops usually used by compilers for VLIW machines. This paper discusses the Cydra 5 loop scheduling model, the special architectural features which support it, and the loop compilation techniques used to take full advantage of the architecture.

High speed scalar processing is an essential characteristic of high performance general purpose computer systems. Highly concurrent execution of scalar code is difficult due to data dependencies and conditional branches. This paper proposes an architectural concept called guarded instructions to reduce the penalty of conditional branches in deeply pipelined processors. A code generation heuristic, the decision tree scheduling technique, reorders instructions in a complex of basic blocks so as to make efficient use of guarded instructions. Performance evaluation of several benchmarks are presented, including a module from the UNIX kernel. Even with these difficult scalar code examples, a speedup of two is achievable by using conventional pipelined uniprocessors augmented by guard instructions, and a speedup of three or more can be achieved using processors with parallel instruction pipelines.

article TIDBITS: speedup via time-delay bit-slicing in ALU design for VLSI technology Share on Authors: Peter Y. T. Hsu Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champalgn Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-ChampalgnView Profile , Joseph T. Rahmeh Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champalgn Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-ChampalgnView Profile , Edward S. Davidson Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champalgn Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-ChampalgnView Profile , Jacob A. Abraham Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champalgn Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-ChampalgnView Profile Authors Info & Claims ACM SIGARCH Computer Architecture NewsVolume 13Issue 3June 1985 pp 29–35https://doi.org/10.1145/327070.327121Online:01 June 1985Publication History 5citation474DownloadsMetricsTotal Citations5Total Downloads474Last 12 Months6Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access