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Paddy Mamtora

dblp:32/1844 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › design validation
functional validation		 0.011993
Experiences in Functional Validation of a High Level Synthesis System · DAC 1993
Electronic design automation
high-level synthesis		 0.011993
Experiences in Functional Validation of a High Level Synthesis System · DAC 1993
Electronic design automation
hardware verification and test		 0.011993
Experiences in Functional Validation of a High Level Synthesis System · DAC 1993
Electronic design automation › hardware verification and test › functional verification
testbench generation		 0.011993
Experiences in Functional Validation of a High Level Synthesis System · DAC 1993

Methods — techniques the papers use, named apart from their topics

specification language analysis · 0.0automated test result comparison · 0.0
YearPublicationVenuePosition
1993 Experiences in Functional Validation of a High Level Synthesis System
abstract
The goal OJ functional validation of a high-level synthesis system is to a$sert, with a reasonable degree of confidence, that the layouta generated by the high-level synthesis system correctly implement the ~pecified behavior.This paper presents a systematic approach to functional validation baaed on the analysis of specification language constructs, de8ign example formation to cover combinations of constructs, ted-bench generation and automated te8t re8u!t comparison.we have 8ucce88.fu![y applied thi8 approach in validating a high-level 8ynthe8i8 8 stem, called 33 DSS, which accepta specifications stated in VI-I L. This effort Te8u[ted in the development of a functional validation suite corssiding of 29 design ezample.s. 1
Ranga Vemuri, Paddy Mamtora, Praveen Sinha, Nand Kumar, Jayanta Roy, Raghu Vutukuru
 DAC2