Recently, digital ICs with high current slewing characteristics and tight supply voltage margin put increasing demand on the supply regulators. In this paper, an augmented DC-DC buck converter consisting of a lower-frequency main converter and a normally-off fast-switching secondary stage operating in parallel is proposed. The main-stage of the converter uses emulated-current-mode hysteretic control. For the auxiliary transient-suppression stage a nonlinear control scheme termed multiple-single-cycle nonlinear control (MSCNLC) is developed. The proposed augmented regulator improves the load transient response without compromising the overall efficiency of the converter, breaking the well-known efficiency vs. dynamic response trade-off. The high power-efficiency main-stage operating at$F_{sw}=500$kHz provides the steady-state DC regulation voltage. The auxiliary-stage adopts a small inductor of 100nH and is only activated when load transient events are detected, providing fast load response, minimizing output voltage deviation. The load transient events are detected through an output capacitor charge tracking circuit, which effectively makes the auxiliary-stage a fast Current-Controlled-Current-Source during transient response. The buck converter is designed for$V_{IN} =3$V-5.5V,$V_{OUT} =0.5$V-1.1V and$I_{LOAD} =0.5$A-8A. It is fabricated in$0.18~\mu $m BCD process. The measurement results show that with MSCNLC enabled, the undershoot and overshoot is reduced to 27mV and 58mV during the step-up and step-down response with 2.5A load step by a factor of close to 2, respectively. The recovery time is improved by ~1.7x.

There is a significant demand in systems-on-chip (SoCs) for a high-power efficiency low-dropout regulator (LDO) that provides lower dropout voltage, higher load current, and low quiescent current. A high-power supply rejection ratio (PSRR) at the mid-to-high frequency band (0.1–10 MHz) is crucial for LDO to generate low-noise power supplies when driven by switching power converters. However, this presents a significant challenge to enhancing the PSRR since the pass field-effect transistor (FET) operates in the deep triode region at high-current and dropout conditions. In this article, a parallel feed-forward current ripple rejection (PFFCRR) technique is proposed to improve the PSRR performance regardless of the operation region of the nMOS pass FET. The proposed approach senses the supply-induced current ripple and cancels the original ripple through a current path that runs parallel to the nMOS pass FET. The proposed LDO is fabricated in a 180-nm BCD process. The proposed LDO achieves a PSRR better than −35 dB up to 10 MHz at 300-mV dropout voltage with 0.5-A load current and a load capacitor of$2.2~\mu $F. The PFFCRR approach achieves a PSRR improvement of 18 dB at 1 MHz at 100-mV dropout voltage with a 2.15-A load current when the pass FET operates in the deep triode region. Moreover, the proposed LDO enhances the transient performance with an overshoot and an undershoot of 40.54 and 36.45 mV, respectively, against$\Delta {I}_{\text {LOAD}}$of 1 A with a slew rate of 1 A/$\mu $s.

The load transient response and unity gain bandwidth of DC-DC boost converters are primarily restricted by the presence of a right half plane zero (RHPZ). In this paper, a control scheme termed peak current fast feedback control (PFFC) is proposed to improve the load transient response without the need for additional power switches or passive components. In the proposed PFFC method, the closed loop output impedance ($Z_{OCL}$) is improved by reducing the DC value and by increasing the bandwidth of$Z_{OCL}$as compared to conventional peak current mode control (CPCM), thus improving the steady state and transient performance. The fast feedback (FFB) path is implemented within the error amplifier (EA) with an increase of only 2% in the active area as compared to CPCM. The boost converter is designed for$V_{OUT} =5\text{V}$,$V_{IN} =2.5\text{V}$-4.4V and$I_{LOAD} =10$mA-1A operating at a fixed frequency of 2MHz. Measurement results show that with PFFC enabled, the settling time reduces by$\sim 2.6\times $and the undershoot reduces by 62% to$12~\mu \text{s}$and 41mV respectively when compared to CPCM for 10mA to 1A load step at 2A/$\mu \text{s}$. The converter achieves a peak efficiency of 95.2% at 0.5W output power with$V_{IN} =4.4\text{V}$and load regulation of 9mV/A at$V_{IN} =2.5\text{V}$.

Robustness to electromagnetic interference (EMI) is one of the primary design aspects of state of the art automotive ICs like System Basis Chips (SBCs) which provide a wide range of analog, power regulation and digital functions on the same die. One of the primary sources of conducted EMI on the Local Interconnect Network (LIN) driver output is an integrated switching DC-DC regulator noise coupling through the parasitic substrate capacitance of the SBC. In this paper an adaptive active EMI cancellation technique to cancel the switching noise of the DC-DC regulator on the LIN driver output to ensure electromagnetic compatibility (EMC) is presented. The proposed active EMI cancellation circuit synthesizes a phase synchronized cancellation pulse which is then injected onto the LIN driver output using an on-chip tunable capacitor array to cancel the switching noise injected via substrate. The proposed EMI reduction technique can track and cancel substrate noise independent of process technology and device parasitics, input voltage, duty cycle and loading conditions of the DC-DC switching regulator. The EMI cancellation system is designed and fabricated on a 180nm Bipolar-CMOS-DMOS (BCD) process with an integrated power stage of a DC-DC buck regulator at a switching frequency of 2MHz along with an automotive LIN driver. The EMI cancellation circuit occupies an area of 0.7 mm2, which is less than 3% of the overall area in a standard SBC and consumes 12.5 mW of power and achieves 25 dB reduction of conducted EMI in the LIN driver output’s power spectrum at the switching frequency and its harmonics.

With increasing diversity of supply chains from design to delivery, there is an increasing risk that unauthorized changes can be made within an IC. One of the motivations for this type of change is to learn important information (such as encryption keys, spreading codes) from the hardware, and transmit this information to a malicious party. To evade detection, such unauthorized communication can be hidden within legitimate bursts of transmit signal. In this article, we present several signal processing techniques to detect unauthorized transmissions which can be hidden within the legitimate signal. We employ a scheme where the legitimate transmission is configured to emit a single sinusoidal waveform. We use time and spectral domain analysis techniques to explore the transmit spectrum. Since every transmission, no matter how low the signal power is, must have a spectral signature, we identify unauthorized transmission by eliminating the desired signal from the spectrum after capture. Experiment results show that when spread spectrum techniques are used, the presence of an unauthorized signal can be determined without the need for decoding the malicious signal. The proposed detection techniques need to be used as enhancements to the regular testing and verification procedures if hardware security is a concern.

Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High-frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency and smaller form factor. Unfortunately, they are also subject to higher process variations, and faster in-field degradation, jeopardizing stable operation of the power supply. This article presents a technique to track changes in the dynamic loop characteristics of DC-DC converters without disturbing the normal mode of operation using a white noise–based excitation and correlation. Using multiple points for injection and analysis, we show that the degraded part can be diagnosed to take remedial action. White noise excitation is generated via a pseudo-random disturbance at reference, load current, and pulse-width modulation (PWM) nodes of the converter with the test signal energy being spread over a wide bandwidth, without significantly affecting the converter noise and ripple floor. The impulse response is extracted by correlating the random input sequence with the disturbed output generated. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the-shelf power converter, LM27402, is used as the device-under-test (DUT) for experimental verification. Experimental results show that the proposed technique can estimate converter natural frequency and quality factor ( Q -factor) within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance. For the diagnosis purpose, a measure of inductor's DC resistance (DCR) value, which is the inductor's series resistance and indicative of the degradation in inductor's Q -factor, is estimated within less than ±1.6% error margin.

Digital low-dropout (DLDO) regulators are gaining attention due to their design scalability for distributed multiple voltage domain applications required in state-of-the-art system-on-chips. Due to the discrete nature of the output current and the discrete-time control loop, the steady-state response of the DLDO has inherent output voltage ripple. A hybrid DLDO (HD-LDO) with fast response and stable operation across a wide load range while reducing the output voltage ripple is proposed. In the HD-LDO, a DLDO and a low current analog ripple cancellation amplifier (RCA) work in parallel. The output dc of the RCA is sensed by a 2-bit analog-to-digital converter, and the digitized linear stage current is fed into the DLDO as an error signal. During load transients, a gear-shift controller enables fast transient response using dynamic load estimation. The DLDO suppresses the output dc of the RCA within its current resolution. With this arrangement, a majority of the dc load current is provided by the DLDO and the RCA supplies ripple cancellation current. The HD-LDO is designed and fabricated in a 180-nm CMOS technology, and occupies 0.697 mm2of the die area. The HD-LDO operates with an input voltage range of 1.43-2.0 V and an output voltage range of 1.0-1.57 V. At 100-mA load current, the HD-LDO achieves a current peak efficiency of 99.11% and a settling time of 15 clock periods with a 0.5-MHz clock for a current switching between 10 and 90 mA. The RCA suppresses fundamental, second, and third harmonics of the switching frequency by 13.7, 13.3, and 14.1 dB, respectively.

A fully integrated digital low-dropout regulator (DLDO) with a fast transient response, providing a regulated supply for system-on-chip (SoC) power management applications is proposed. Wideband operation and fast transient response are achieved through a transient enhanced proportional-integral controller, without compromising the stability of the DLDO at steady-state operation. The transient enhancement stage boosts loop-gain dynamically during load transients. In the gain boosting mode, the DLDO closed-loop bandwidth is increased, resulting in reduced undershoot/overshoot and fast settling. When the output voltage recovers to the desired level, the boost mode operation is disabled. For a load change with a 4-mA/ns slew rate between 10 and 50 mA, utilizing transient enhancement mode reduced the measured undershoot and overshoot by 35% and 17%, respectively. The characterization results show that the transient enhancement mode can reduce the settling time from 500 to 250 ns for a 10-50-mA load current change. The proposed DLDO operates with an input voltage ranging from 0.84 to 1.24 V, and output voltage ranging from 0.6 to 1 V. The maximum output current of the DLDO is 50 mA and the DLDO achieves a peak current efficiency of 99.2%, with DLDO figure of merit (FOM2) of 63.25 ps. The DLDO prototype chip is fabricated on a 0.13-μm CMOS technology and occupies a 0.0631-mm2die area.

Failure due to aging mechanisms in CMOS devices is an important concern of RF circuits. Lifetime of analog/RF circuits is defined as the point where at least one specification will fail due to aging effects. In this brief, we present a methodology for analyzing the performance degradation of RF circuits caused by aging mechanisms in MOSFET devices and inductors at design time (presilicon). We identify reliability hotspots and concentrate on these circuit components to enhance the lifetime with low area and no performance impact.

Efficient, stable, and fast power delivery against fluctuating workloads have become a critical concern for applications from battery-powered devices to high-performance servers. With high density on-chip capacitors, fully-integrated switched-capacitor (SC) voltage converters provide high efficiency down-conversion from a battery or off-chip voltage regulation modules. However, maintaining such efficiency with minimal supply noise across a wide range of fluctuating load currents remains challenging. In this paper, we propose an on-chip current sensing technique to dynamically modulate both switching frequency and switch widths of SC voltage converters, enhancing fast transient response and higher efficiency across a wide range of load currents. In conjunction with SC converters, we employ a low-dropout regulator (LDO) driven by a push-pull operational transconductance amplifier (OTA), whose current is mirrored and sensed with minimal power and efficiency overhead. The sensed load current directly controls the frequency and width of SC converters through a voltage-controlled oscillator (VCO) and a time-to-digital converter, respectively. In 32nm SOI CMOS, the proposed voltage regulator maintains 77-82% efficiency at 0.95V output voltage with less than 20mV steady-state ripple across 10X load current range of 100mA-1A and 33mV droop voltage for a 80mA/ns load transition, while providing a projected current density of 6W/mm2.

Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency. Unfortunately, they are also subject to higher process variations jeopardizing stable operation of the power supply. This paper presents a technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal energy being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the-shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.

With increasing diversity of supply chains from design to delivery, there is an increasing risk of unauthorized changes within an IC. One of the motivations for this type change is to learn important information (such as encryption keys, spreading codes) from the hardware and pass this information to a malicious party through wireless means. In order to evade detection, such unauthorized communication can be hidden within legitimate bursts of transmit signal. In this paper, we present a stealth circuit for unauthorized transmissions which can be hidden within the legitimate signal. A CDMA-based spread spectrum with a CDMA encoder is implemented with a handful of transistors. We show that the unauthorized signal does not alter the circuit performance while being easily detectable by the malicious receiver.

Several state-of-the-art monitoring and control systems, such as dc motor controllers, power line monitoring and protection systems, instrumentation systems, and battery monitors, require direct digitization of high-voltage (HV) input signals. Analog-to-digital converters (ADCs) that can digitize HV signals require high linearity and low-voltage coefficient capacitors. A built-in self-calibration and digital-trim algorithm correcting static mismatches in capacitive digital-to-analog converter (DAC) used in successive approximation register analog-to-digital converters (SAR ADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit HV input range SAR ADC with integrated DEC capacitors. The IC is fabricated in 0.6-μm HV-compliant CMOS process, accepting up to 24Vppdifferential input signal. The proposed approach achieves 73.32-dB signal-to-noise and distortion ratio, which is an improvement of 12.03 dB after self-calibration at 400-kS/s sampling rate, consuming 90 mW from a ±15 V supply. The calibration circuitry occupies 28% of the capacitor DAC and consumes2.

Failure due to aging mechanisms is an important concern for RF circuits. In-field aging results in continuous degradation of circuit performances before they cause catastrophic failures. In this regard, the lifetime of RF/analog circuits, which is defined as the point where at least one specification fails, is not just determined by aging at the device level, but also by the slack in the specifications, process variations, and the stress conditions on each of the devices. In this paper, we present a methodology for analyzing, monitoring, and mitigating performance degradation in cross-coupled LC oscillators caused by aging mechanisms in MOSFET devices. At design time, we identify reliability hot spots and concentrate our efforts on improving these components. We aim at altering degradation patterns of important performance parameters, thereby improving the lifetime of the circuit with low area and no performance impact. We use simulations based on verified aging models to evaluate the monitoring and mitigation techniques and show that the proposed methods can increase the lifetime of the devices with no impact on the initial performance.

One of the major problems associated with integrated DC-DC converters used in state of the art Power Management ICs (PMICs) is dynamic performance and stability degradation due to off-chip component and output current variations. A high accuracy built-in self-test (BIST) architecture measuring load inductance and DC resistance (DCR) of DC-DC converters is presented. The DCR measurement of the inductor also enables continuous, lossless average load current sensing of the DC-DC converter across the inductor. Both the BIST circuit and the primary signal chain utilize low analog complexity frequency-domain ΔΣADC. The ΔΣADC decimation filter nulls also provide current ripple cancellation and average current extraction. The BIST module can measure filter inductance values ranging from 3.6μH to 22.3μH range with average 2.0% error and inductor DCR 13mΩto 68mΩ range with average 2.1% error. The average current sensing enabled by the BIST technique achieves current measurement accuracy with average 2.3% error for 0.1A-1A range load current. BIST and current sensing modules occupy less than 6% of total chip area. The BIST circuitry is fabricated and tested with a 12V input, 1V-11.5V output range, for a 3W output power digital DC-DC converter.

Power management units are essential parts in almost every electronic system. PMUs have distinct test and calibration schemes compared to other regular analog circuits since they operate in the large signal mode and the operation heavily depends on the nature of the load. Built-in test and calibration for PMUs is becoming increasingly more common-place due to the challenges posed by increasing process variations, decreasing form factor, and increasingly diverse load conditions. This panel will discuss the challenges related to testing of power management circuits, calibration and built-in test approaches that are currently in place and the way to move forward.

Testing and calibration of MEMS devices require physical stimulus, which results in the need for specialized test equipment and thus high test cost. It has been shown for various types of sensors that electrical stimulation can be used to facilitate lower cost calibration. In this paper, we present an electrical stimulus based test and calibration technique for overdamped spring-mass capacitive accelerometers which require the characterization of stationary and dynamic calibration coefficients. We show that these two coefficients can be electrically obtained.

A step-down (buck) switching converter architecture that makes use of switched capacitors to improve the transient response is presented. Using the proposed architecture, the transient response is improved by a factor of two or more in comparison to the theoretical limits that can be achieved with a basic step down architecture. The architecture presented in this paper can be used for both analog and digitally controlled topologies. Simulation results of a 1.8V, 15W, 1MHz digitally controlled step down converter with a 12mV ADC resolution and a 2ns DPWM resolution are presented.

Designing high linearity phase-frequency-detectors (PFDs) in low-voltage, deep submicrometer processes is a challenging problem. Nonlinear PFDs can fold out of band phase noise, and increase in-band phase noise of fractional-N PLLs in deep submicron processes. A 3-GHz Type-I ΣΔ fractional-N PLL with an exponentially settling voltage-mode switched-RC phase frequency detector (PFD) is presented. A voltage-mode, fully settled switched-RC (SRC)-based sample-and-hold PFD, providing benefits of both an RC loop-filter and a zero-order hold sinc( ) suppressing reference clock leakage is presented. The exponentially settled SRC PFD is shown to reduce the in-band leakage of quantization noise by 13 dB in comparison to a similar current-mode charge pump PFD, enabling a measured loop-bandwidth of 890-kHz. The fractional-N PLL is fabricated in a 180-nm CMOS technology with 6 metal layers and consumes 18-mA from a 1.8-V power supply. The worst-case near-integer in-band spur is measured at -62 dBc. The measured in-band phase noise at 100-kHz offset from the 3-GHz carrier is -107 dBc/Hz and out-of-band phase noise at 3-MHz offset is -130 dBc/Hz. The phase-locked loop settling time for a frequency step of 45-MHz and 0.1-ppm accuracy is less than 10-μs.

The design and development of analog/mixed-signal (AMS) ICs is becoming increasingly expensive, complex, and lengthy. Lacking a reconfigurable platform, analog designers are denied the benefits of rapid prototyping, hardware emulation, and smooth migration to advanced technology nodes. To overcome these limitations, this work proposes a new approach that maps any AMS design problem to a transistor-level reconfigurable vehicle, thus enabling fast validation and a reduction in post-Silicon bugs, and minimizing design risk and costs. The unique features of the approach include: (1) transistor-level programmability that emulates each transistor behavior in an analog design, reproducing the system and achieving very fine granularity of reconfiguration; (2) programmable switches that are treated as a design component during analog transistor mapping, and optimized with the reconfiguration matrix; (3) parasitics reduction that leverages the aggressive scaling of CMOS technology. Based on these principles, a digitally controlled PANDA platform is designed at a 32nm node. Several 90nm analog blocks are successfully emulated with the 32nm platform, including a folded-cascode operational amplifier, a sample-and-hold module (S/H), and a voltage-controlled oscillator (VCO). A solid basis to future efforts on the architecture, hierarchical optimization, and related design automation tools is demonstrated.

A 10 b opamp-sharing pipeline analog-to-digital (A/D) using current-reuse operational transconductance amplifiers (OTA) with dual nMOS differential inputs is presented. The current-reuse OTA topology facilitates opamp-sharing between all of the consecutive pipeline stages, minimizing power consumption and die area. Analog transistors in the OTA are always biased in saturation ensuring no loss of settling time due to OTA power turn-on delays. The A/D is fabricated in a 0.18-$\mu$m CMOS process and occupies an active die area of 0.7 mm$^{2}$. At 50 MS/s, maximum SNDR of 58 dB$({\rm ENOB}={\hbox {9.3 b}})$is achieved with 9.2 mW analog power consumption on a 1.8 V supply.

A technique for power-bandwidth scaling of a current feedback amplifier (CFA) is presented. By employing current gain, instead of the feedback resistance, to alter the closed-loop bandwidth of the CFA, the proposed approach is shown to provide 30% quiescent power savings for a bandwidth variation of 10MHz to 100MHz. Parasitic extracted simulations are performed in a 0.18μm CMOS process with a power supply of 3.3V and a load capacitance of 1.5pF. A closed-loop gain range of 0-20dB, slew rate of 200V/μs, settling time of 33ns and total harmonic distortion of 73dB is achieved at a quiescent power consumption range of 3mW to 4.4mW.

A radix-3, 4-trits, Ternary Successive Approximation Analog to Digital Converter (TSAR-ADC), with an option to extend to radix-N approaches is presented. Proposed TSAR-ADC architecture generates 4 ternary outputs spanning 34= 81 binary levels linearly for a rail-to-rail input voltage ranging from 0 to 3.3V. The radix-3 TSAR-ADC takes only 4 clock cycles for producing 4-trits or 6.33 bits in comparison to 7 clock cycles in a conventional binary SAR converter. The ADC is designed and fabricated on a 0.35μm double poly, three level metal CMOS technology, achieving less than 1 LSB INL, 0.8 LSB of DNL, consuming 1.6-mW from a 3.3-V supply.

A workload-aware low-power neuromorphic controller for dynamic voltage scaling in VLSI systems is presented. The neuromorphic controller predicts future workload values and preemptively regulates supply voltage based on past workload profile. Our specific contributions include: (1) implementation of a digital and analog version of the controller in 45nm CMOS technology, resulting in 3% performance hit with a power overhead in the range of 10-150 microwatts, (2) higher prediction accuracy compared to a software based OS-governed DVS scheme by 50%, reducing wasted power and improving error margins, (3) digital design has minimal power overhead and is more reconfigurable, while analog design is better suited for nonlinear and complex computational tasks.

Resonant clock distribution with distributed LC oscillators is promising to reducing clock power and jitter noise. Yet the difficulty in the integration of on-chip inductors still limits its application in practice. This paper resolves such a key issue with sub-50 ¿m magnetic inductors, which are fully compatible with the CMOS process. These inductors leverage soft magnetic coils to achieve inductances up to 4nH, Q-factor of 3 at 1 GHz with a device diameter of only 30-50 ¿m, resulting in area savings of nearly 100X as compared to conventional design. The latency and noise performance of the resonant clock network is demonstrated to be comparable to those using conventional inductors without soft magnetic materials. In addition, inductors with integrated magnetic materials significantly reduce mutual coupling and eddy current loss in the power grid below the clock network. These design advantages enable high density of on-chip distributed oscillators, providing better phase averaging, lower power and superior noise characteristics as compared to traditional buffer-tree based clock network.

As CMOS technology scales down, digital supply voltage and digital power consumption goes down. However, the supply voltage and power consumption of the RF front-end and analog sections do not scale in a similar fashion. In fact, in many state-of-the-art communication transceivers, RF and analog sections can consume more energy compared to the digital part. In this paper, first, a system level energy model for all the components in the RF and analog front-end is presented. Next, the RF and analog front-end energy consumption and communication quality of three representative systems are analyzed: a single user point-to-point wireless data communication system, a multi-user code division multiple access (CDMA)-based system and a receive-only video distribution system. For the single user system, the effect of occupied signal bandwidth, peak-to-average ratio (PAR), symbol rate, constellation size, and pulse-shaping filter roll-off factor is analyzed; for the CDMA-based multi-user system, the effect of the number of users in the cell and multiple access interference (MAI) along with the PAR and filter roll-off factor is studied; for the receive-only system, the effect of 1/f noise for direct-conversion receiver and the effect of IF frequency for low-IF architecture on the RF front-end power consumption is analyzed. For a given communication quality specification, it is shown that the energy consumption of a wireless communication front-end can be scaled down by adjusting parameters such as the pulse shaping filter roll-off factor, constellation size, symbol rate, number of users in the cell, and signal center frequency

Abstract This paper discusses the implementation of an automatic antenna tuning unit system (ATU) for software‐defined and cognitive radio. The ATU simplifies radio frequency (RF) front‐end design for multi‐band, multi‐mode radios by allowing an electrically small reconfigurable antenna to become a frequency‐agile selective component (essentially a tunable filter). In implementing the ATU, impedance synthesizers (tunable matching networks) using RF MEMS switches as the control elements are used to match a more or less arbitrary load to a convenient impedance value. To generate feedback data that can be used to optimize the impedance synthesizer, the incident and reflected powers at the input to the impedance synthesizer are sampled using a power sensor block comprising directional coupler, logarithmic RF power detectors, analog‐to‐digital converters (ADCS), and return loss computation algorithms running on a field programmable gate array (FPGA). From a practical point of view, in order to be compatible with commercial wireless handset devices, we propose to design and ultimately implement a fully integrated ATU system. In this paper, a hard‐ ware implementation of the ATU prototype has been demonstrated to verify narrowband automatic tuning ability of the ATU under constantly changing environment conditions, and we present simulated results for a logarithmic power detector designed with 55 dB dynamic range over the 800 MHz–2 GHz frequency band using 0.25 µ CMOS technology. Copyright © 2007 John Wiley & Sons, Ltd.

Design and analysis of a fully integrated two-stage interleaved synchronous buck DC-DC converter with on-chip filter inductor and capacitor is presented. The DC-DC converter is designed and fabricated in a 0.18 mum SiGe RFBiCMOS process technology and generates 1.5V-2.0V programmable output voltage supporting a maximum output current of 200mA. High switching frequency, multi-phase interleaved operation, and fast hysteretic controller reduce the filter inductor and capacitor sizes by two orders of magnitude compared to the state-of-the-art converters and enable a fully integrated converter. The fully integrated buck regulator achieves 64% efficiency while providing an output current of 200 mA

Pulse width modulation (PWM) and sigma delta modulation (SDM) have been used in several high linearity, high accuracy power delivery applications such as DC-DC power converters, audio and RF power amplifiers as well as in data converters. In this paper, we present a particular class of carrier frequency modulated PWM (CFMPWM), which spreads the tonal content of regular PWM uniformly in frequency and reduces the baseband noise with respect to SDM by up to 15 dB. The new modulation scheme preserves at the same time the high efficiency properties of PWM. An approximate method to estimate the spectrum of CFMPWM signals with both deterministic and random modulation is also presented. Simulation results and experimental data are reported to analyze the spectral spreading properties of the proposed CFMPWM scheme.

A 0.16 mW, 2.3 Volt multi-channel digitally controlled oscillator (MDCO) core is designed in a 0.6 micron CMOS process and its prototype design is mapped on an Altera FPGA that can be used for clock recovery applications. This architecture is suitable for digital wireless and cable transceivers that use different bands for transmit and receive modes. As crystal-based-delay cells control its dominant propagation delay, we have obtained a reduced phase-noise in comparison to recently published analog-based DCOs.