This paper draws on a 2-week design workshop conducted at a rural primary school in northern India to provide recommendations on carrying out participatory design with school children in rural, underdeveloped regions. From our experiences in prototyping low-tech and hi-tech English language learning games with rural student participants, we advocate that researchers build a more equal relationship that is qualitatively different from one between teachers and students, enlist local adults and children as facilitators, and explore hi-tech prototyping to inspire the best designs.

Block cyclic redundancy check (CRC) codes represent a popular and powerful class of error detection techniques used almost exclusively in modern data communication systems. Though efficient, CRCs can detect errors only after an entire block of data has been received and processed. In this work, we exploit the "continuous" nature of error detection that results from using arithmetic codes for error detection, which provides a novel tradeoff between the amount of added redundancy and the amount of time needed to detect an error once it occurs. We demonstrate how this continuous error detection framework improves the overall performance of communication systems, and show how considerable performance gains can be attained. We focus on several important scenarios: 1) automatic repeat request (ARQ) based transmission; 2) forward error correction (FEC frameworks based on (serially) concatenated coding systems involving an inner error-correction code and an outer error-detection code; and 3) reduced state sequence estimation (RSSE) for channels with memory. We demonstrate that the proposed CED framework improves the throughput of ARQ systems by up to 15% and reduces the computational/storage complexity of FEC and RSSE by a factor of two in the comparisons that we make against state-of-the-art systems.

Summary form only given. This work introduces a multiple-description product code which aims at optimally generating multiple, equally-important wavelet image descriptions from an image encoded by the popular SPIHT image coder. Because the SPIHT image coder is highly sensitive to errors, forward error correction is used to protect the image against bit errors occurring in the channel. The error-correction code is a concatenated channel code including a row (outer) code based on RCPC codes with CRC error detection and a source-channel column (inner) code consisting of the scalable SPIHT image coder and an optimized array of unequal protection Reed-Solomon erasure-correction codes. By matching the unequal protection codes to the embedded source bitstream using our simple, fast optimizer, we maximize expected image quality and provide for graceful degradation of the received image during fades. To achieve unequal protection, each packet is split into many Reed-Solomon symbols. The i/sup th/ symbol in each packet forms an (n,k) Reed-Solomon code or "column". A fast, nearly-optimal optimizer, based on Lagrange multipliers and optimal to within convex hull and discretization approximations, chooses k for each Reed-Solomon "column" to minimize the expected mean-square error at the receiver. We validated our use of this structure by evaluating its performance in the context of transmitting images over a wireless fading channel. The performance of this scheme was evaluated by simulating the transmission of the Lena image over a Clarke flat-fading channel with an average SNR of 10 dB and a normalized Doppler frequency of 10/sup -5/ Hz.

Intersymbol interference (ISI) distorts digital signals transmitted over band-limited channels. While solutions like decision feedback equalization (DFE) suffer from error propagation, sequence estimation methods have exponential complexity. We present a scheme that effectively reduces the complexity of sequence estimation by removing paths that are in error on the fly, using continuous error detection (CED). The number of symbols taken for detecting an error can be tuned based on the amount of redundancy available for the particular application. Simulations show that our scheme can bring about a factor of two reduction in complexity in the trellis of Yellin, Vardy and Amrani (see IEEE Trans. on Info. Theory, vol.43, p.409-25, 1997) and give about 0.5 dB performance improvement at the same complexity. CED can be implemented efficiently at low complexity in hardware and can enhance the performance of ARQ/FEC based digital transmission systems. This work presents the performance gains in a reduced state sequence estimation framework.