A novel Reinforcement Learning (RL) approach, that uses sequence-based placement representations and ensemble learning, is proposed for Monolithic 3D IC (M3D) placement. Our algorithm successfully chooses one of the best of the four types of placement perturbation actions most of the time. A New Ensemble-based policy allows to use multiple learning algorithms to choose good actions. RL produces an initial solution for Simulated Annealing (SA) that generates the final answer. To illustrate the effectiveness of SERS-3DPlace, we tested it on 8-128-bit MUX-based right arithmetic shifter (Muxs) circuits and a circuit with non-regular connections, as compared to Mux-based shifters, all implemented in 2-layer Monolithic 3D technology. The experimental results show that the Ensemble-based policy performs 2.5X better than the Multilayer Perceptron (MLP)-based policy, and the new SERS-3DPlace shows 2X improvement in the RL stage over RS3DPLace [1].

We propose a novel Reinforcement Learning (RL) and Simulated Annealing (SA)-based placement algorithm (RS3DPlace), which, to the best of our knowledge, is the first machine learning approach for Monolithic 3D ICs (M3D). Application of Machine Learning to physical design of 2D and 3D VLSI ICs is an emerging area. Recently proposed learning algorithms for the placement problem consider only 2D ICs and still exhibit memory issues and learning problems in large search spaces. RS3DPlace uses the learning ability of RL to quickly estimate a preliminary solution, which SA later uses to generate an improved final solution. To address memory issues, RS3DPlace uses the approximate method for state representation which reduces the memory complexity and allows more than one kind of perturbation to improve learning efficiency in large search spaces. The current implementation is for the gate-level M3D design style, but it can be extended to other M3D design styles and other 2D and 3D physical design optimization problems. To illustrate the effectiveness of RS3DPlace, we tested it for 8-128-bit MUX-based right arithmetic shifter circuits and a circuit with non-regular connections compared to Mux-based shifters, which are optimized in 2-layered M3D technology. The experimental results show that RS3DPlace solves the M3D placement of 896 variables. Experimental results also show on average 16% improvement in overall cost function in comparison to Random Initialized SA (RandSA).

Carbon nanotube field-effect transistors (CNFETs) show great potential to build digital systems on advanced technology nodes with big benefits in terms of power, performance, and area (PPA). However, CNFET-specific additional features such as the number of tubes, pitch (spacing between tubes), tube position, and diameter in array of tubes play a significant role in accurate PPA evaluation. Furthermore, count and density variations in carbon nanotubes (CNTs) due to manufacturing limitations, like the presence of metallic tubes in the CNFET channel, degrade the anticipated PPA benefits. Moreover, modeling the CNFET parameters, CNT variations and etching techniques for CNTs create additional complexity during performance optimization. Hence, for realistic optimization of CNFET circuit's performance, it is imperative to incorporate the impact of these parameters and variations. In this paper, we propose delay models [pitch-aware logical effort (PALE) and position-aware pitch factor (PAPF)] for fast and accurate performance evaluation by including the impact due to CNFET-specific parameters and CNT variations. These models are developed based on industry standard logical effort framework. Furthermore, we present an optimization tool using PALE and PAPF to minimize the delay and area of CNFET circuits. We deploy several circuit-level techniques prior to optimizing the tubes (CNTs) in the logic gates to achieve globally optimum solution. For better optimization of the circuits, we also include the impact of wire parasitic in estimating the delay of the individual gates. Our optimization tool results in the maximum and average delay improvement by 27% and 17%, respectively, and 2.5× reduction in area for standard ISCAS and OpenSPARC benchmark circuits. Fast and fairly accurate delay computation in our optimization framework offers great runtime benefits as compared to state-of-the-art simulation and statistical-based methods.

We generate, then analyse and evaluate the buffered interconnect performance and power dissipation in 3DICs with vertical temperature distribution. Wire distribution in all device layers in 3D ICs is generated at the floorplanning level. The floorplanner optimizes simultaneously blocks' and TSV islands' locations to reduce delay and power. We assume a heat sink is located at the bottom of the stack and temperature increases up the stacked layers. We noticed that weak increase in wire delay with temperature reduces the buffer insertion length and rises the number of needed buffers. More buffers with a considerable increase in buffer delay and leakage power impacts interconnect performance. It is shown that without including vertical temperature profile a prediction of 3D ICs performance and power dissipation could be strongly over- or underestimated. It also means that quality of 3D layout solutions generated during early optimization stages of physical design can be questionable. The percentage of overestimation and underestimation depend on location of the heatsink, the temperature profile and the benchmark itself. In tested benchmarks, we noticed up to 55% underestimation of the interconnect delay, 31 % in buffer count and 63% and higher in interconnect power consumption as compared to typically used room-temperature interconnect parameters' values.

We propose a new scheme of dynamic nets-to-TSVs assignment during floorplanning for 3D-ICs. A nontrivial area occupied by TSVs, their physical dimensions, location on the layout and the nets-to-TSVs assignment, are some of the key factors influencing the wirelength, TSV count and chip area, and consequently, impact the total delay. We address the above issues by simultaneous placement of TSV islands with circuit blocks, assignment of nets to TSV islands during floorplanning and directly optimizing interconnect delay. TSVs induce significant thermo-mechanical stress in nearby silicon, and to reduce the impact of stress, we incorporate pitch and Keep-Out-Zone (KOZ) around TSVs in our approach. The proposed dynamic nets-to-TSVs assignment approach, improves solution compared to a previously used fixed nets-to-TSVs assignment, by achieving on average 6-9% delay reduction. Analysis for various TSV aspect ratios using the proposed assignment method is also presented.

We are assessing the effect of our new freshman electrical engineering course sequence on follow-on courses. One of our assessments is a survey distributed to sophomores in electrical circuits and juniors in microelectronics courses. Roughly one half of freshman year is spent on programming in MATLAB and C, and problem solving using these programming tools. Our observation is that students consider programming important and have reasonably good confidence (self-efficacy) that they can solve problems using MATLAB and C. However, when asked about frequency of use for these tools students report using them somewhere between once a week and once a month. There is a significant number of students who report almost no usage at all. Results are consistent across sophomore and junior years with a slight up-tick in frequency of use for juniors. We are hypothesizing that students do not view MATLAB and C as tools for problem solving but as yet another item to acquire in their studies. Our plan is to change instruction in sophomore courses so that more problem-solving which requires programming will be introduced. The existing survey will be used to measure future improvement.

This paper presents a comprehensive analysis of the impact of CNT fabrication imperfections on the performance of multichannel Carbon Nanotube FET (CNFET) -based devices. In particular, we introduce a methodology for stochastically estimating the impact of spacing between adjacent tubes and the impact of its variation. This enables accurate prediction of the reduction in drive current due to the removal of tubes, the increase in spacing between adjacent tubes, and variations in tube diameter and spacing. In multichannel CNFETs, when the number of channels (CNTs) is greater than eight, our experiments show that variations in tube diameter and inter-tube spacing result in less than 8% performance variation. Monte Carlo simulation results, however, show that the removal of tubes increases variation in IONfrom 13% to 26% due to larger variation in inter-tube spacing. The presented realistic analysis and the proposed methodology can be extremely useful in variation-tolerant CNFET-based circuit design.

We present a placement-aware 3-D floorplanning algorithm that considers 3-D-placement of logic gates inside modules for wirelength minimization. It allows designers to introduce and evaluate an assignment of vertically-aligned parts of the same module to different device layers. A set of vertical constraints is derived on sequence pairs of different device layers that reduces the solution space, and a fast packing algorithm with vertical constraints enables quick floorplan evaluation. Experimental results on MCNC and GSRC benchmarks show that our algorithm can generate a good floorplanning solution with reduced wirelength inside modules and optimized footprint area while controlling the number of vias. Compared to the existing state-of-the-art 3-D floorplanning algorithms, our tool reduces the system level total wirelength by 9.8%.

We present a novel 3D floorplanning algorithm with module splitting (3D-FMS). The proposed methodology allows designers to introduce and evaluate an assignment of vertically-aligned parts of the same module to different device layers. Our experimental results on MCNC and GSRC benchmarks show that 3D-FMS can generate a good floorplanning solution with reduced wirelength inside modules and optimized footprint area while controlling the number of vias. Compared to the existing state-of-the-art 3D floorplanning algorithms, 3D-FMS reduces the system level total wirelength by 7.9%.

Carbon Nanotube FET (CNT-FET) is a promising candidate for the construction of future integrated circuits. However the presence of metallic tubes negatively affects delay, leakage power, and yield of such circuits. In this paper we compare four different CNT-FET configurations - shared tube, parallel tubes, transistor stacking, and tube stacking. In the presence of 10% metallic tubes, stacking configurations have potential to as much as double the yield for 4.1-4.4X delay penalty under iso-input capacitance and 3-7X lower leakage power compared to the non-stacked configurations. Analytical model and Monte Carlo simulation results for various logic gate sizes clearly indicate that an architecture that utilizes an appropriate combination of all four configurations is required to enable a better trade-off between delay, leakage power, and yield in the presence of metallic tubes.

Noise generated by digital sub-circuits becomes a serious problem in fast mixed signal system on chips (SoCs). Digitally generated noise corrupts supply voltages and is propagated inside a silicon substrate as so called substrate noise. The circuits for substrate noise suppression proposed so far have serious weaknesses due to their frequency limitations. We present a method for optimization of noise-suppressive active circuits to improve their properties at high frequencies, illustrate efficiency of the optimization procedure an example of an active circuit consisting of a single voltage gain stage and a buffer is designed and tested by means of simulations. The improved circuits show over 9 dB better substrate noise attenuation at frequencies above 1 GHz in comparison to known passive and active solutions.

Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-based method that makes uses of structural analysis, integrated simulation and Boolean satisfiability for fast and scalable detection of classical symmetries of completely-specified Boolean functions. This is in contrast to previous incomplete circuit-based methods and complete BDD-based methods. Experimental results demonstrate that the proposed method works for large Boolean functions, for which BDDs cannot be constructed.

An analytical method for power supply spectrum estimation to be used in early system planning is proposed. The method is based on a careful evaluation of a number of parameters of an equivalent inverter; rise time, fall time and widths of current impulses. We assume an inverter to be a basic building component of digital blocks. Using the proposed method one can determine estimates of power supply noise levels and characteristic frequencies in its spectrum

Simulation and Boolean satisfiability (SAT) checking are common techniques used in logic verification. This paper shows how simulation and satisfiability (S&S) can be tightly integrated to efficiently compute flexibilities in a multilevel Boolean network, including the following: 1) complete "don't cares" (CDCs); 2) sets of pairs of functions to be distinguished (SPFDs); and 3) sets of candidate nodes for resubstitution. These flexibilities can be used in network optimization to change the network structure while preserving its functionality. In the first two applications, simulation quickly enumerates most of the solutions while SAT detects the remaining solutions. In the last application, simulation efficiently filters out most of the infeasible solutions while SAT checks the remaining candidates. The experimental results confirm that the combination of simulation and SAT offers a computation engine that outperforms binary decision diagrams, which are traditionally used in such applications.

This paper describes linear cofactor relationships (LCRs), which are defined as the exclusive sums of cofactors with respect to a pair of variables in Boolean functions. These relationships subsume classical symmetries and single-variable symmetries. The paper proposes an efficient algorithm to detect LCRs and discusses their potential applications in Boolean matching, minimization of decision diagrams, synthesis of regular layout-friendly logic circuits, and detection of support-reducing bound sets

We propose a frequency-dependent sensitivity model for analog blocks and a noise injection model for digital blocks in application to early design planning of Mixed-Signal System-on-Chips (MS-SOCs). We assume no precise layout information about IP cores is available. We also propose an empirical formula for separation-dependent coupling between large-area noisy ports and small-area sensitive ports for lightly-doped substrates that are preferred for mixed-signal circuits. The interaction between digital and analog blocks is incorporated into our floorplanner, which reduces the overall noise and the number of analog blocks with noise limit violations. Experimental results on examples created from MCNC floorplanning benchmarks are very encouraging.

Detecting support-reducing bound sets is an important step in Boolean decomposition. It affects both the quality and the runtime of several applications in technology mapping and re-synthesis. This paper presents an efficient heuristic method for detecting support-reducing bound sets using two-cofactor symmetries. Experiments on the MCNC and ITC benchmarks show an average 40x speedup over the published exhaustive method for bound set construction.

A new evolutionary algorithm to co-optimize test scheduling and wrapper design under power constraint for core-based SoCs is presented. Core testing solutions are generated as a set of. wrapper designs, each represented as a rectangle with width equal to the test time and height equal to the number of TAM wires used. The test-scheduling problem under power constraint is formulated as the bin-packing problem. We solve the problem using an evolutionary strategy and sequencepair representation. Experiments on ITC’OZ benchmarks show that, for most examples, our algorithm generates better solutions than previous approaches.

A new approach to the interconnect-driven floorplanning problem integrates bus planning and is intended for bus-based designs where each bus consists of a large number of wires. The floorplanner optimizes the timing and ensures routability by generating the exact location and shape of interconnects above and between the circuit blocks. Experiments with Microelectronics Center of North Carolina benchmarks clearly show the advantage of integrated floorplanning over the classical floorplan-analysis-and-then-refloorplan approach. Our floorplans are routable, meet all timing constraints, and are on average 12%-13% smaller in area as compared to traditional floorplanning algorithms.

This paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in the digital design of clos-folded field-programmable gate array (FPGA) based logic emulation systems. The approach transforms the FPGA board-level routing task into a Boolean equation. Any assignment of input variables that satisfies the equation specifies a valid routing. We use two of the fastest Boolean satisfiability (SAT) solvers: Chaff and DLMSAT to perform our experiments. Empirical results show that the method is time-efficient and applicable to large layout problem instances.

We introduce a new procedure for constructing nonslicing floorplans with soft modules. The procedure uses an evolution strategy to place hard modules, after which the final best placement is relaxed. The procedure is computationally efficient and our results surpass recently published results using the MCNC benchmarks.

The paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in Clos-Folded FPGA based logic emulation systems. The approach transforms the FPGA board-level routing task into a single, large Boolean equation with the property that any assignment of input variables that satisfies the equation specifies a valid routing. The approach considers all nets simultaneously and the absence of a satisfying assignment implies that the layout is unroutable. We use two of the fastest SAT solvers: Chaff and DLM to perform our experiments. Empirical results show that the method is time-efficient and applicable to large layout problem instances.

A new approach to the interconnect-driven floorplanning problem that integrates bus planning with floorplanning is presented. The integrated floorplanner is intended for bus-based designs. Each bus consists of a large number of wires. The floorplanner ensures routability by generating the exact location and shape of interconnects (above and between the circuit blocks) and optimizes the timing. Experiments with MCNC benchmarks clearly show the superiority of integrated floorplanning over the classical floorplan-analyze-and-then-re-floorplan approach. Our floorplans are routable, meet all timing constraints, and are on average 12-13% smaller in area as compared to the traditional floorplanning algorithms.

Reversible logic is of increasing importance to many future computer technologies. We introduce a regular structure to realize symmetric functions in binary reversible logic. This structure, called a 2*2 net structure, allows for a more efficient realization of symmetric functions than the methods introduced by the other authors. Our synthesis method allows us to realize arbitrary symmetric function in a completely regular structure of reversible gates with relatively little "garbage". Because every Boolean function can be made symmetric by repeating input variables, our method is applicable to arbitrary multi-input multi-output Boolean functions and realizes such arbitrary function in a circuit with a relatively small number of additional gate outputs. The method can also be used in classical logic. Its advantages in terms of numbers of gates and inputs/outputs are especially seen for symmetric or incompletely specified functions with many outputs.

This paper introduces a new design approach that combines logic and layout synthesis for Cellular-Architecture (CA) FPGAs. The comprehensive design method starts from a Boolean function, specified as SOP or ESOP, and produces a rectangularly-shaped multi-level structure of (mostly) locally connected cells. This twodimensional array of logic cells is well suited for CA-type FPGA realization. Two stages: restricted factorization and technology folding are discussed in more details. The architecture constraints and the implementation are presented for ATMEL6000 series architecture. 1.

The work described in this paper is a component of our comprehensive approach to the low-level synthesis (logic synthesis and layout synthesis) of Cellular-Architecture (CA-type) FPGAs. A multiple-output logic function is represented as a collection of complex terms. Each term is assigned to a separate row of a CA-type FPGA. These terms are collected using EXOR or OR gates to create function outputs, initially one output per column. In this paper an algorithm for multiple column folding of CA-type FPGAs is presented. The formulation of the problem is similar to the gate matrix layout problem but with additional constraints. Experimental results are very encouraging.>

A program for the minimization of multi-output three-level Boolean networks from NAND gates of unlimited fan-in is described. This model includes don't care states. The algorithm is fast and creates good-quality approximate solutions, and its efficiency increases with the percentage of don't cares. It has been tried on about 40 Boolean functions of not more than 14 inputs, and yielded correct results. The realized circuits (on PLH501 and PLH502 PLDs) required up to 68% (on the average 35%) less gates than the corresponding PLAs. The program can consider tradeoffs between the solution-cost and the processing speed by using various type of the source data.>