The Network-on-Chip (NoC) serves as the critical communication backbone in modern Multi-Processor Systems-on-Chip (MPSoCs), particularly for Deep Learning (DL) hardware where it underpins the reliable execution of machine learning models by facilitating efficient data and weight exchange. However, the NoC is vulnerable to stealthy packet-based attacks initiated by malicious Intellectual Property (IP) cores. Such attacks can severely degrade NoC latency and throughput, which are critical for efficient DL inference, and even compromise the correctness of model execution. Current detection methods are inherently reactive; they identify anomalies by monitoring global system features only after an attack has manifested, lacking the foresight to anticipate impending threats. To address this, we propose Pack Defender, a proactive NoC security framework based on temporal behavior modeling that forecasts future system states and reuses its partial prediction generative model for detection, eliminating the need for a separate module. Experimental results show strong predictive power, with average/top-three similarities of 83%/92% for Source-Level Packet Dropping (SLPD) and 90%/94% for In - Network Packet Diversion (INPD). The low Mean Absolute Error (0.05 for SLPD, 0.03 for INPD) further confirms its accuracy. The detection model (XGBoost) achieves 100% accuracy, with recall rates of 96% and 99% for SLPD and INPD respectively, significantly outperforming state-of-the-art methods lacking proactive prediction.

The software product is a source of cyber-attacks that target organizations by using their software supply chain (SSC) as a distribution vector. As the reliance of software projects on open-source or proprietary modules is increasing drastically, SSC is becoming more and more critical and, therefore, has attracted the interest of cyber attackers. While existing studies primarily focus on software supply chain attacks’ prevention and detection methods, there is a need for a broad overview of attacks and comprehensive risk assessment for software supply chain security. This study conducts a systematic literature review to fill this gap. By analyzing 96 papers published between 2015-2023, we identified 19 distinct SSC attacks, including 6 novel attacks highlighted in recent studies. Additionally, we developed 25 specific security controls and established a precisely mapped taxonomy that transparently links each control to one or more specific attacks. By establishing this relationship, we demonstrate how SSC security controls are strategically designed to counteract specific attack vectors. Furthermore, we emphasize the role of risk assessment as a foundational step in understanding and prioritizing these vulnerabilities. This study introduces a risk assessment methodology tailored to software supply chain environments, focusing on identifying vulnerabilities in software components, dependencies, and suppliers. The proposed methodology enables organizations to systematically prioritize threats and implement appropriate mitigation strategies.

This study introduces a refined Flooding Injection Rate-adjustable Denial-of-Service (DoS) model for Network-on-Chips (NoCs) and more importantly presents DL2Fence, a novel framework utilizing Deep Learning (DL) and Frame Fusion (2F) for DoS detection and localization. Two Convolutional Neural Networks models for classification and segmentation were developed to detect and localize DoS respectively. It achieves detection and localization accuracies of 95.8% and 91.7%, and precision rates of 98.5% and 99.3% in a 16×16 mesh NoC. The framework's hardware overhead notably decreases by 76.3% when scaling from 8×8 to 16×16 NoCs, and it requires 42.4% less hardware compared to state-of-the-arts. This advancement demonstrates DL2Fence's effectiveness in balancing outstanding detection performance in large-scale NoCs with extremely low hardware overhead.

As convolutional neural networks (CNNs) gain traction for embedded device implementation, there’s a burgeoning interest in approximate computing technologies for increasing hardware efficiency. Most of the works in this field focus on proposing novel approximate hardware units and structures, but structured guidance for selecting optimal approximate calculation techniques for CNN accelerators remains scant. This paper introduces a novel error injection technique, leveraging the error rate matrix of approximate multipliers (AxMs), called Error Matrix Based Error Injected (EMEI). This facilitates the swift selection of appropriate AxMs for each PE in the CNN hardware accelerator. In addition, this approach is applied to a MobileNetV2-based CNN model on the CIFAR-10 dataset to demonstrate the performance. Experimental results show that our method adeptly optimises hardware resources by combining AxMs with different accuracy levels while ensuring accuracy. This innovation paves the way for streamlined CNN accelerator designs in embedded systems.

Flying ad hoc networks (FANETs) are collections of Unmanned Aerial Vehicles (UAVs) or nodes which deliver network services to areas lacking fixed infrastructure. The protocols controlling the flow of data in these ad hoc networks are prone to cyber attacks. In this paper, we consider cyber attacks in the form of probabilistic packet dropping or grey hole attacks which are executed by compromised nodes within the network. The defence protocols used to thwart this attack are usually evaluated in restricted environments with a low range of packet dropping attacks. To remedy this, we propose a new competitive evaluation framework, MANET-Rank, which uses empirical game theoretic analysis and bootstrapping to assess the effectiveness of defence protocols in ad hoc networks. Specifically, game theory is used to strategically assess the most effective protocol whilst bootstrapping generates an effective ranking metric from a small number of simulations. To assess the effectiveness of MANET-Rank, we conduct a comparative analysis of two previously proposed protocols by comparing the results of MANET-Rank and those generated by established evaluation methods. As a result, we demonstrate that MANET-Rank yields superior conclusions.

Networks-on-Chips (NoC) based Multi-Processor System-on-Chip (MPSoC) are increasingly employed in industrial and consumer electronics. Outsourcing third-party IPs (3PIPs) and tools in NoC-based MPSoC is a prevalent development way in most fabless companies. However, Hardware Trojan (HT) injected during its design stage can maliciously tamper with the functionality of this communication scheme, which undermines the security of the system and may cause a failure. Detecting and localizing HT with high precision is a challenge for current techniques. This work proposes for the first time a novel approach that allows detection and high-precision localization of HT, which is based on the use of packet information and machine learning algorithms. It is equipped with a novel Dynamic Confidence Interval (DCI) algorithm to detect malicious packets, and a novel Dynamic Security Credit Table (DSCT) algorithm to localize HT. We evaluated the proposed framework on the mesh NoC running real workloads. The average detection precision of 96.3% and the average localization precision of 100% were obtained from the experiment results, and the minimum HT localization time is around 5.8 ~ 12.9us at 2GHz depending on the different HT-infected nodes and workloads.

Network-on-Chip (NoC) is becoming an increasingly common System-on-Chip (SoC) fabric architecture since it matches the characteristics of the SoC's shared storage and high-frequency communication. However, due to the rising utilization of NoC, a large number of adversaries are trying to inject Hardware Trojan (HT) into NoC to obtain profits. An increasing variety of NoC HTs is emerging and implemented, resulting in current detection methods becoming invalid. This paper presents a cascaded machine learning model based Denial-of-Service (DoS) attack detection and classification approach. An Support Vector Machine (SVM) and a K-Nearest Neighbor (KNN) model were employed in the framework, which has also been validated on our runtime mixed dataset consisting of normal and attacked data extracted from four traffic pattern cases. The proposed framework achieved an expected detection accuracy: more than 85% on detection in average. And outstanding classification results on every attack: 97% on Flooding, and up to 100%on both Routing Loop and Traffic Diversion.

Physically Unclonable Functions (PUFs) are cryptographic primitives used to implement low-cost device authentication and secure secret key generation. Weak PUFs (i.e., devices able to generate a single signature or to deal with a limited number of challenges) and Strong PUFs (i.e., devices able to deal with large number of challenges) are widely discussed in literature. Strong PUFs are susceptible to machine learning and modeling attacks. In this paper we propose a solution where the challenges of a Strong PUF are encrypted in order to remove the linear challenge-response correlation that can be exploited by those attacks. In this context, a ZeroBit Error Rate Weak PUF generates the encryption key so that all PUF instances have a different, nonlinear correlation between respective challenges and responses. We present two implementations of the proposed solution, and we demonstrate their resilience against machine learning attacks.

CMOS wear-out mechanisms, especially Bias Temperature Instability (BTI), have caused growing concerns about circuit reliability. For cache memories, BTI reduces the static noise margin (SNM), causing unreliable read operations. In practice, error-correction codes (ECCs) are often used to protect data from transient errors in caches, but the limited error correction capabilities are not always enough to overcome BTIinduced read failures. In this paper, we propose a cell flipping technique with distributed refresh phases (CFDR) to minimize cache degradations. The CFDR method flips and refreshes each cache block at different times, minimizing the interruption time and balancing the degradation rate, even for infrequently replaced cache blocks. We evaluate the CFDR technique on an instruction cache in a 32-bit ARM architecture and show our method reduces the number of error bits by 58.86% and 13.59%, compared with an ECC scheme and a traditional cell flipping technique. The cache lifetime can be improved by 125% by using CFDR with less than 1% area overhead, which is not only more effective but also more cost-efficient than the existing techniques.

Physical Unclonable Functions (PUFs) exploit the intrinsic manufacturing process variations to generate a unique signature for each silicon chip; this technology allows building lightweight cryptographic primitive suitable for resource-constrained devices. However, the vast majority of existing PUF design is susceptible to modeling attacks using machine learning technique, this means it is possible for an adversary to build a mathematical clone of the PUF that have the same challenge/response behavior of the device. Existing approaches to solve this problem include the use of hash functions, which can be prohibitively expensive and render PUF technology as the suitable candidate for lightweight security. This work presents a challenge permutation and substitution techniques which are both area and energy efficient. We implemented two examples of the proposed solution in 65-nm CMOS technology, the first using a delay-based structure design (an Arbiter-PUF), and the second using sub-threshold current design (two-choose-one PUF or TCO-PUF). The resiliency of both architectures against modeling attacks is tested using an artificial neural network machine learning algorithm. The experiment results show that it is possible to reduce the predictability of PUFs to less than 70% and a fractional area and power costs compared to existing hash function approaches.

Embedded systems suffer from reliability issues such as variations in temperature and voltage, single event effects and component degradation, as well as being exposed to various security attacks such as control hijacking, malware, reverse engineering, eavesdropping and many others. Both reliability problems and security attacks can cause the system to behave anomalously. In this paper, we will present a detection technique that is able to detect a change in the system before the system encounters a failure, by using data from Hardware Performance Counters (HPCs). Previously, we have shown how HPC data can be used to create an execution profile of a system based on measured events and any deviation from this profile indicates an anomaly has occurred in the system. The first step in developing a detector is to analyse the HPC data and extract the features from the collected data to build a forecasting model. Anomalies are assumed to happen if the observed value falls outside a given confidence interval, which is calculated based on the forecast values and prediction confidence. The detector is designed to provide a warning to the user if anomalies that are detected occur consecutively for a certain number of times. We evaluate our detection algorithm on benchmarks that are affected by single bit flip faults. Our initial results show that the detection algorithm is suitable for use for this kind of univariate time series data and is able to correctly identify anomalous data from normal data.

Delay-fault monitoring sensors are widely used for Dynamic Voltage and Frequency Scaling (DVFS) to compensate for intrinsic Process, Voltage, Temperature and Ageing (PVTA) variations. Such techniques are generally based on monitoring the circuit’s critical paths. This paper presents a new delay-fault monitoring circuit, which is able to monitoring multiple paths simultaneously. The proposed circuitry has been designed and verified in a 32 bit MIPS processor using a 65nm technology. Our results indicate that the use of the proposed sensor for delay monitoring can lead to a significant saving in area and power overheads of two-thirds and one-third, respectively, compared to a canary flip-flop.

Hysteresis in a comparator improves the input noise immunity, but can also cause analogue single event transients (ASETs) to be captured. For example, compared to a hysteresis-free comparator, a comparator with a hysteresis voltage of 8 mV, takes an additional 40 ns to recover. As the requirement for noise immunity increases, the vulnerability of a comparator with hysteresis to ASETs worsens. The reliability also worsens for higher sampling frequencies and lower differential input voltage amplitudes. This paper investigates the trade-off between noise immunity and reliability in a 65nm CMOS comparator.

This paper provides a comprehensive evaluation of the effects of Bias Temperature Instability (BTI) aging on the delay of level shifters. The latter are indispensable blocks in energy efficient systems with multiple supply voltages. Our results show that conventional level-up shifters exhibit significantly more aging-induced delay degradation compared to standard logic cells. Our experiments performed in a predictive 32nm technology indicate those designs can suffer from more than 200% increase in their delay after 5 years due to BTI aging compared to an average of 20% delay rise in the case of standard CMOS logic. Our investigations show that the reason behind this phenomenon is the differential signaling structure present in the majority of conventional level up shifters, combined with the use of low supply voltages.

Silicon Physical Unclonable Functions (PUFs) have emerged as novel cryptographic primitives, with the ability to generate unique chip identifiers and cryptographic keys by exploiting intrinsic manufacturing process variations. The “Two Choose One” PUF (TCO-PUF) has recently been proposed. It is based on a differential architecture and exploits the non-linear relationship between current and voltage in the subthreshold operating region. As CMOS technology scales down, aging-induced Negative Bias Temperature Instability (NBTI) is becoming more pronounced, resulting in reliability issues for the PUF response. Differential design techniques can be useful for mitigating and canceling out first-order environmental dependencies such as aging, temperature and supply voltage. In this study, we investigate the robustness of PUFs with differential architectures, such as TCO-PUF and Arbiter-PUF, under the influence of NBTI. Our results indicate PUFs with differential architectures are less vulnerable to aging-related degradation compared to other PUF designs such as RO-PUF and SRAM-PUF. We show that the reliability of TCO-PUF and Arbiter-PUF only degrades by about 4.5% and 2.41%, respectively, after 10 years, while RO-PUFs and SRAM-PUFs degrade by about 12.76% in 10 years and 7% in 4.5 years, respectively.

The aggressive scaling of semiconductor technology has significantly increased the radiation-induced soft-error rate in modern microprocessors. Meanwhile, due to the increasing complexity of modern processor pipelines and the limited error-tolerance capabilities that previous radiation hardening techniques can provide, the existing pipeline protection mechanisms cannot achieve complete protection. This paper proposes a complete and cost-effective pipeline protection mechanism using a self-checking architecture. The radiation-hardened pipeline is achieved by incorporating soft-error- and timing-error-tolerant flip-flop (SETTOFF)-based self-checking cells into the sequential cells of the pipeline. A replay recovery mechanism is also developed at the architectural level to recover the detected errors. The proposed pipeline protection technique is implemented in an OpenRISC microprocessor in a 65-nm technology. A gate-level transient fault-injection and analysis technique is used to evaluate the error-tolerance capability of the proposed hardened pipeline design. The results show that compared with the techniques such as triple modular redundancy, the SETTOFF-based self-checking technique requires over 30% less area and 80% less power overheads. Meanwhile, the error-tolerant and self-checking capabilities of the register allow the proposed pipeline protection technique to provide a noticeably higher level of reliability for different parts of the pipeline compared with the previous pipeline protection techniques.

Physical Unclonable Functions (PUF) is an emerging design technology for secure hardware. It exploits the physical manufacturing variations of silicon ICs to generate a unique signature for each chip. A Ring Oscillator (RO) based PUF is a promising solution for the authentication of FPGA devices. However; this technique has not yet been widely adopted due to its large area costs and the lack of platform-independent PUF architectures which are “easy to implement”. Existing RO PUF design requires large number of ring oscillators to generate a relatively safe unique identifier; they also have complex routing requirements. This work proposes a novel configurable RO PUF architecture easily portable between different FPGA platforms. It also offers significantly larger number of challenge-response pairs compared to existing solutions with the same area overheads. The design was realized and characterized using an Altera FPGA device. Experimental results show that the quality of this design conforms to the requirements of general RO PUF.

The aggressive scaling of semiconductor devices has caused a significant increase in the soft error rate caused by radiation hits. This has led to an increasing need for fault-tolerant techniques to maintain system reliability. Conventional radiation hardening techniques, typically used in safety-critical applications, are prohibitively expensive for non-safety-critical electronics. This work proposes a novel flip-flop architecture named SETTOFF which significantly improves circuit resilience to radiation hits over previous techniques. In addition, compared to other techniques such as a TMR latch, SETTOFF reduces the area and performance overheads by up to 50% and 80%, respectively; the power consumption overhead is also reduced by up to 85%. In addition, a novel reliability metric called radiation-induced failure rate is developed which can be a valuable tool to predict the impact of radiation hits and quantitatively compare the reliability of various radiation hardened techniques. Our analysis shows that the proposed technique can achieve zero SEU failure rate, and significantly reduce the SET failure rate.

The effect of crosstalk avoidance codes on the throughput of fixed width communication channels is studied. Closed form expressions of the throughput which incorporate the dimensions of the interconnects and the wiring overheads incurred by such techniques are derived for lines under different buffering conditions. These formulae are utilized to optimize the bandwidth of constrained-area parallel buses under different latency and power constraints. Our results are confirmed by the simulations we have performed in Spectre for a UMC CMOS 90-nm technology.

The effect of crosstalk avoidance codes on the throughput of fixed width communication channels is studied. Closed form expressions of the throughput which incorporate the dimensions of the interconnects and the wires overheads by such techniques are derived for lines under different buffering conditions. These formulae are utilised to optimise the bandwidth of fixed width parallel buses under different latency and reliability constraints. Our results are confirmed by the simulations we have performed in Spectre for a UMC CMOS 90 nm technology.

An on-chip intermodule self-timed communication system is considered in which symbols are encoded by means of phase difference between transitions of signals on parallel wires. The reliability of such a channel is governed and significantly lowered by capacitive crosstalk effects between adjacent wires. A more robust high-speed phase-encoded channel can be designed by minimizing its vulnerability to crosstalk noise. This paper investigates the impact of crosstalk on phase-encoded transmission channels. A functional fault model is presented to characterize the problem. Two fault-tolerant schemes are introduced which are based on information redundancy techniques and a partial-order coding concept. The area overheads, performance, and fault-tolerant capability of those methods are compared. It is shown that a substantial improvement in the performance can be obtained for four-wire channels when using the fault-tolerant design approach, at the expense of 25 percent of information capacity per symbol.