Neural networks are known to be universal computers for Boolean functions. Recent advancements in hardware have significantly reduced matrix multiplication times, making neural network simulation both fast and efficient. Consequently, functions defined by complex Boolean networks are increasingly viable candidates for simulation through their neural network representation. Prior research has introduced a general method for deriving neural network representations of Boolean networks. However, the resulting neural networks are often suboptimal in terms of the number of neurons and connections, leading to slower simulation performance. Optimizing them while preserving functional equivalence --lossless optimization-- is an NP-hard problem, and current methods only provide lossy solutions. In this paper, we present a deterministic algorithm to optimize such neural networks in terms of neurons and connections while preserving functional equivalence. Moreover, to accelerate the compression of the neural network, we introduce an objective-aware algorithm that exploits representations that are shared among subproblems of the overall optimization. We demonstrate experimentally that we are able to reduce connections and neurons by up to 70% and 60%, respectively, in comparison to state-of-the-art. We also find that our objective-aware algorithm results in consistent speedups in optimization time, achieving up to 34.3x and 5.9x speedup relative to naive and caching solutions, respectively. Our methods are of practical relevance to applications such as high-throughput circuit simulation and placing neurosymbolic systems on the same hardware architecture.

We propose a new learning framework, signal propagation (sigprop), for propagating a learning signal and updating neural network parameters via a forward pass, as an alternative to backpropagation (BP). In sigprop, there is only the forward path for inference and learning. So, there are no structural or computational constraints necessary for learning to take place, beyond the inference model itself, such as feedback connectivity, weight transport, or a backward pass, which exist under BP-based approaches. That is, sigprop enables global supervised learning with only a forward path. This is ideal for parallel training of layers or modules. In biology, this explains how neurons without feedback connections can still receive a global learning signal. In hardware, this provides an approach for global supervised learning without backward connectivity. Sigprop by construction has compatibility with models of learning in the brain and in hardware than BP, including alternative approaches relaxing learning constraints. We also demonstrate that sigprop is more efficient in time and memory than they are. To further explain the behavior of sigprop, we provide evidence that sigprop provides useful learning signals in context to BP. To further support relevance to biological and hardware learning, we use sigprop to train continuous time neural networks with the Hebbian updates and train spiking neural networks (SNNs) with only the voltage or with biologically and hardware-compatible surrogate functions.

Register Transfer Level (RTL) simulation and verification of Digital Circuits are extremely important and costly tasks in the Integrated Circuits industry. While some simulators have incorporated the exploitation of parallelism in the structure of Digital Circuits to run on multi-core CPUs, the maximum throughput they achieve quickly reaches a plateau, as described by Amdahl’s Law. Recent research from Nvidia has obtained much higher throughput in simulations using GPUs, highlighting the potential of these devices for Digital Circuit simulation. However, they were required to incorporate sophisticated algorithms to support GPU simulation. In addition, the unbalanced structure of real-life Digital Circuits provides difficulties for processing on multi-threaded devices. In this paper, we present a Digital Circuit compiler that utilizes Neural Networks to exploit the various parallelisms in RTL simulation, making use of PyTorch, a widely-used Neural Network framework that facilitate their simulation on GPUs. By using properties of Boolean Functions, we developed a novel algorithm that converts any Digital Circuit into a Neural Network, and optimization techniques that help in pushing the thread computational capability to the limit. The results show three orders of magnitude higher throughput than Verilator RTL simulator, an improvement of one order of magnitude compared to the state-of-the-art GPU techniques from Nvidia. We believe that the use of Neural Networks not only provides a significant improvement in simulation and verification tasks in the Integrated Circuits industry, but also opens a line of research for simulators at the logic and physical gate level.

Digital circuits are the basic structure of most of today's electronic devices. Simulation plays a critical role in the iterative development of such circuits as a consequence of the time and financial expenses that accompany fabrication. There are existing tools that achieve simulation by modeling circuits with Hardware Description Languages (HDL). However, with recent advances in neural networks (NN) and hardware accelerators for NN simulation, a niche of digital circuit simulation via NNs has opened up. Here, we introduce C2NN (Circuit to Neural Network), a novel method that converts (or transpiles) any digital circuit expressed in a HDL into a NN for simulation. The conversion to a NN representation not only affords the benefits of parallelization, the use of GPUs for simulation, and optimizations such as pruning, but it also provides a methodology for achieving equivalent digital circuit computation in neuromorphic hardware. We describe the transpilation process of C2NN and verify its correctness on small- and large-scale digital circuits. We also found that the simulation time of the transpiled circuits is competitive with one of the fastest digital circuit simulators.

We use evolutionary search to automatically find electronic circuits that oscillate, i.e., that periodically toggle an output line from low to high. Reconfigurable hardware in the form of field programable gate arrays (FPGA's)-as opposed to circuit simulation-computes a circuit's fitness which guides the evolutionary search. We find empirically that oscillating circuits can be evolved that closely approximate target frequencies specified a priori. Our evolved oscillators alias a harmonic of the target frequency to satisfy the fitness goal. Frequencies of the evolved oscillators are sensitive to temperature and to the physical piece of silicon in which they operate. Such sensitivities have negative implications for deployment of evolved circuits in conventional applications, but may have positive implications for adaptive computing. We observe that operating the FPGA's transistors at voltages below specification often increases the number and quality of evolved solutions.

Experimental results from adaptive learning using an optically controlled neural network are presented. The authors have used example problems in nonlinear system identification and signal prediction, two areas of potential neural network application, to study the capabilities of analog neural hardware. These experiments investigated the effects of a variety of nonidealities typical of analog hardware systems. They show that network using large arrays of nonuniform components can perform analog communications with a much higher degree of accuracy than might be expected given the degree of variation in the network's elements. The effects of other common nonidealities, such as noise, weight quantization, and dynamic range limitations, were also investigated.

The proximity effect, caused by electron-beam backscattering during resist exposure, can be compensated for by appropriate local changes in the incident beam dose, but the optimal correction, found iteratively, requires a prohibitively long time for realistic pattern sizes. A neural network has been used to perform these corrections, resulting in a significant decrease in computation time. The correction was first computed for a small test pattern using an iterative method. This solution was used as a training set for an adaptive, feedforward neural network, using back-propagation learning. After training, the network computed the same correction as the iterative method, but in a much shorter time