System-on-Wafer (SoW) technology integrates multiple chiplets onto a single wafer substrate, offering enhanced performance for high-computation applications. This paper presents an innovative 3D test access architecture designed for complex SoW systems. The proposed omnidirectional test access architecture, compliant with IEEE Std. 1838, provides a scalable, plug-and-play testing solution for comprehensive multi-directional testing. It enables efficient scan path configuration, optimizing test scheduling while reducing power consumption and minimizing timing-related impacts. A case study involving a SoW system with four chiplets arranged in a 2x2 configuration validates the architecture's feasibility and effectiveness, demonstrating its potential to enhance SoW testability and reliability.

Choosing a DfT architecture for heterogeneous multi-core SoCs is constrained by various business, design and industrial-test requirements. SSN is a bus-based packetized data distribution scan architecture designed to address these requirements. A comparison between SSN and previous hierarchical DfT approaches is shown. A specific project SoC requirements is reviewed with packetized scan delivery architecture trade-offs. Results show 2X scan data transfer rate while adhering to pinning, area and physical design constraints.

This paper proposes a new framework for inserting test points at RTL (Register Transfer Level) enabling better Power-Performance-Area-Testability (PPAT) optimization during synthesis and yielding quick turn-around time and faster Time-to-Market (TTM). It introduces the concept of editable nodes in RTL designs and avoids locations that are difficult to modify. Early identification of editable nodes in the RTL to guide and drive the test point analysis engine helps in improving the quality of test points inserted into the design. In addition, the proposed methodology involves optimization of the RTL, a quick synthesis of the design, and test point analysis at the netlist-level by avoiding locations that are pre-marked as ‘don't-touch’. Once the test point locations are identified in an internal unmapped gate representation, they are back annotated and inserted in the RTL. Some locations can be directly mapped back, whereas some other locations can be mapped back to expression and sub-expression boundaries in RTL with the help of additional information that is exported during the logic synthesis step. Experimental results on several industrial designs show that the effectiveness of test points inserted at RTL closely matches their counterparts at the gate-level with added benefits of better area, timing, test coverage, and pattern count optimization early in the design flow.

Under the functional safety standard ISO26262, automotive systems require testing in the field, such as the power-on self-test (POST) . Unlike the production test, the POST requires reducing the test application time to meet the indispensable test quality (e.g., >90% of latent fault metric) of ISO26262. This article proposes a test point insertion technique for multi-cycle power-on self-test to reduce the test application time under the indispensable test quality. The main difference to the existing test point insertion techniques is to solve the fault masking problem and the fault detection degradation problem under the multi-cycle test. We also present the method to identify a user-specified amount of test points that could achieve the most scan-in pattern reduction for attaining a target test coverage. The experimental results on ISCAS89 and ITC99 benchmarks show 24.4X pattern reduction on average to achieve 90% stuck-at fault coverage confirming the effectiveness of the proposed method.

In recent years, low power devices have become widely designed. Since the power supply design is based on the user operation, there is the possibility that it can malfunction in conventional scan testing on account of the excessive power consumption during scan testing. In order to overcome this problem, we have combined and adopted various scan testing techniques. This paper presents a scan testing approach that is demonstrated to be effective for ultra-low power devices. It splits one scan shift clock into several scan shift clocks per clock domain. Moreover, it changes the scan shift clock speed to cope with the inrush current. These clock controls are made possible by our own test clock controller.

Multi-cycle Test applies more than one capture cycles during the capture operation which is a promising way to reduce the test volume of Logic-BIST (Logic Built-in Self-Test) based POST (Power-on Self-Test) for achieving high fault coverage. However, the randomness loss of the capture patterns due to the large number of capture cycles obstructs the further improvement of fault coverage and pattern reduction. In this paper, we propose a novel approach to control the capture patterns by modifying the captured values of scan Flip-Flops (FFs) during capture operation to enhance the test quality of the capture patterns. In the approach, we insert FF-Control circuits between the scan FFs and the combinational circuit to improve the randomness of the capture patterns by loading toggle vectors/pseudo-random vectors. The experimental results of ISCAS89 and ITC99 benchmarks validated the effectiveness of the proposed methods in fault coverage improvement and random pattern reduction for Logic-BIST.

To attain the requirement of ISO26262 standard, the POST for automotive MCU needs to achieve high Latent Fault (LF) metric (>90% for ASIL D) within limited test application time (TAT). In this paper, we propose a new DFT technique named Fault-Detection-Strengthened (FDS) method to enhance the effect of test pattern reduction of the multi-cycle test for shortening the TAT of POST, and develop an original in-house tool named FVP-TPI (Fault Vanishing Point-TPI) to implement the FDS method to automotive MCU. The evaluation results on a latest commercial automotive MCU (62M gates) confirm the effectiveness (test volume compaction) and the practicability (smaller hardware overhead, shorter period of DFT) of the method.

Recently, we must use the various scan test techniques for various purposes, for example, compression scan or LBST for mass-production test, LBIST for field test, legacy scan for fault diagnosis, and so on. Moreover, the number of the available external scan pins is different in each test process, for example, the parallel test process has a low pin count, the assembled chip test process has several pin counts depending on the assembled package types, and so on. Then, the cost-effective scan chain structure is also different for each purpose and each test process. In order to correspond to this situation, we introduce the multi-configuration scan structure which can change the numbers of scan chains. Evaluation result shows that our approach can improve test time for area overhead.

BIST based field testing is a promising way to guarantee the functional safety of intelligent and autonomous systems. To improve the fault coverage with less random patterns for BIST, sequentially observing some flip-flops (FFs) during multi-cycle test is useful. In this paper, we propose the methodology for selecting the Fault-Detection-Strengthened FFs in multi-cycle test by evaluating the structure of a circuit. The experimental results of ITC99 benchmarks and a real Electronic Control Unit (ECU) circuit show the effectiveness of the proposed methods in fault coverage improvement and random pattern reduction.

Today, at-speed test cost comprises a majority of the total test cost of a design. This derives from the fact that if the design has numerous data transfers between clock domains, we must generate test patterns for all of the synchronous data transfers to guarantee high reliability. Conventionally, at-speed test patterns are generated for each of the transfers separately. In order to reduce at-speed test application time, we take an approach to increase the number of the transfers tested concurrently. Evaluation results show that our approach is effective for that purpose.

This paper discusses a low-power test scheme compatible with both test compression and built-in self-test environments. The key contribution is a detailed analysis showing that a simple power-aware controller may allow significant reductions of toggling rates when feeding scan chains with either decompressed test patterns or pseudorandom vectors. While the proposed solution requires minimal modifications of existing DFT logic, its use results in a low switching activity during all phases of scan test: loading, capture, and unloading. It reduces power consumption to or below a level of a functional mode, thus helping to resolve problems related to power dissipation, voltage drop, and increased temperature.

This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce thenotationto analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) thecombinationallytestableclass and 2) theacyclicallytestableclass. Then, we introduce a new class oflinear-depthtime-boundedcircuits as one of the acyclically testable classes. The linear-depth time-bounded testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of flip-flops in the circuit during the test generation process. As one of the linear-depth time-bounded classes, we introduce a new class of RTL circuits, called thecycle-unrollableRTL circuits, which is shown to be linear depth time bounded. We propose a DFT method to make RTL circuits cycle unrollable and a test generation method for cycle-unrollable RTL circuits. Experimental results show that we can drastically reduce hardware overhead and test application time compared to the full-scan method and the method proposed by Ohtake Moreover, our proposed method can achieve 100% fault efficiency for gate-level single stuck-at faults in practical test generation time and allow at-speed testing.

This paper presents a non-scan design-for-testability method for register transfer level circuits. We first introduce a new testability of RTL circuits called partially strong testability. The partially strong testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of registers in the RTL circuit during test generation process. We also propose a DFT method to make RTL circuits partially strongly testable. Experimental results show that we can reduce hardware overhead and test application time drastically compared to the previous methods. Moreover, the proposed method can achieve 100% fault efficiency in practical test generation time and allow at-speed testing.

This paper presents a non-scan design-for-testability (DFT) method that guarantees complete fault efficiency (FE) for register transfer level (RTL) data paths. We first define the partially strong testability as a characteristic of data paths. Then we propose a DFT method to make a data path partially strongly testable and a test generation method for partially strong testable data paths based on the time expansion model (TEM). The proposed DFT method can reduce hardware overhead drastically compared with the previous method based on strong testability. Moreover, the proposed DFT method can generate test patterns with complete FE in practical time and allow at-speed test.