Systematic design of pipelined recursive filters is presented. The procedure is based on a multiplication algorithm which generates the result with most significant digit first. Since the latency of such a multiplier is low, a reduced number of pipelining delays may be introduced in the reduction loop, resulting in a high sampling rate. The implementation obtained exhibits minimum hardware and ensures minimum latency. It is shown that its flexibility allows, on one hand, the ability to choose freely the number system radix and, on the other hand, the interleaving of two multiplier arrays into one. This is illustrated by the realization of a second-order all-pole filter, operating in a radix-4 representation and using only one array to perform two multiplications. In this way, long interconnections are avoided and denser and more regular layout is achieved. It turns out that the design procedure can also be applied successfully to various types of realization where multiplications are required.>

A novel digital implementation of time-domain block LMS (least mean square) filtering is presented. The primitive operators are serial-parallel multipliers which produce the results digit by digit, most significant first. The use of a redundant notation is essential here. These operators are placed in a parallel and pipeline structure, resulting in a fast realization with O(log(L*N) mod /sub L/) time, where N and L are filter length and block length, respectively. This new realization is particularly suitable for VLSI implementation because of this modularity and the high integration capacity of the serial-parallel multipliers.>