Enterprise suppliers are faced with increasing complex tasks of enabling B2B stores to serve their enterprise customers for direct purchases and to support a large number of protocols in order to interoperate with various procurement systems. In this paper, we present a unified B2B solution that separates the integration process into two protocol-dependent and independent tasks with a 2-tier architecture to simplify the support of commerce functions for diverse access points. The first tier B2B gateway system handles all protocol related tasks such as handshaking with external networks and message format conversion. The second tier commerce engine executes commerce related tasks and provides protocol-independent shopping and ordering support for the B2B stores. Using a single sign-on mechanism and a unified shopping cart format in the commerce engine, our solution has streamlines the administrative processes associated with supporting and boarding new B2B buyers into the commerce engine.

A buffer insertion ring with network access fairness control for gigabit LANs is proposed. The basic buffer insertion ring has the maximum spatial reuse on the multiple ring segments by allowing concurrent traffic, but it suffers from the possibility of station starvation. To solve this problem, a notion of adjustable fairness based on mutual interference between pairs of stations in bandwidth usage is defined. The adjustable fairness definition serves as a basis for conditions to trigger backpressure signals. A cooperative backpressure mechanism is invented for flow regulation. The effectiveness of the proposed network access mechanism is demonstrated by comparisons with other buffer insertion rings based on simulations.>

It is shown how to represent the objective function of the memory repair problem as a neural-network energy function, and how to exploit the neural network's convergence property for deriving optimal repair solutions. Two algorithms have been developed using a neural network, and their performances are compared with that of the repair most (RM) algorithm. For randomly generated defect patterns, a proposed algorithm with a hill-climbing capability successfully repaired memory arrays in 98% cases, as opposed to RMs 20% cases. It is demonstrated how, by using very small silicon overhead, one can implement this algorithm in hardware within a VLSI chip for built in self repair (BISR) of memory arrays. The proposed auto-repair approach is shown to improve the VLSI chip yield by a significant factor, and it can also improve the life span of the chip by automatically restructuring its memory arrays in the event of sporadic cell failures during the field use.>

The authors introduce two types of neural networks that can be integrated into array-type very-large-scale integration/wafer-scale integration (VLSI/WSI) chips, allowing them to restructure themselves automatically so that, in the presence of multiple random faults, the array circuits can perform their computations correctly. In the first implementation, the neural network is interconnected and programmed so that it can execute a maximum matching algorithm and thereby substitute appropriate fault-free spare elements for the faulty components. The second implementation rearranges the surviving fault-free processors to restore the logical structure, and it can adjust its interconnection complexity based on the quality of solution (i.e., performance) desired. These two approaches are compared with the traditional reconfiguration algorithms, and by simulation it is shown that the neural network techniques provide superior performance (i.e., higher survivability rates). It is also shown that the intrinsic fault-tolerant nature of neural networks provides a degradable reconfiguration control even in the presence of faulty neural network components.>

The feasibility of implementing electronic neural networks as intelligent hardware for memory array repair is demonstrated. In particular, it is shown that the neural network control possesses a robust and degradable computing capability under various fault conditions. A yield analysis performed on 64K DRAMs shows that the yield can be improved from as low as 20% to near 99% owing to the self-repair design, with an overhead of no more than 7%. Simulation shows that the neural net algorithms are superior to the Repair Most algorithm.>

A neural network model is proposed for circuit bipartitioning. The massive parallelism of neural nets has been successfully exploited to balance the partitions of circuit and to reduce the external wiring between the partitions. The experimental results obtained by neural nets are found to be comparable with those achieved by the C.M. Fiduccia and R.M. Mattheyses (1982) algorithm. The proposed approach can be implemented in hardware to accelerate time-consuming partitioning procedures.>

This paper proposes a neural network model for circuit bipartitioning. The massive parallelism of neural nets has been successfully exploited to balance the partitions of a circuit and to reduce the external wiring between the partitions. The experimental results obtained by neural nets are found to be comparable with that achieved by Fiduccia and Mattheyses algorithm.