Thermal imaging, as a promising approach for scalable and robust scene perception, is invaluable for many applications in various fields, such as architecture and building physics. Despite many recent works having demonstrated their capability to incorporate thermal images into radiance field methods, they typically do not explicitly model how radiation interacts and reflects within the scene before reaching the camera, which is essential for inferring thermal physics and properties of objects in a scene. Using Gaussian primitives as the scene representation, our method estimates surface temperature and material properties to generate infrared renderings that closely match the input images. Taking inspirations from radiosity and hemicube rasterization, our method decomposes the outgoing radiation from each Gaussian primitive into two parts: self-emission and reflection originating from other primitives and the environment. This formulation allows us to simulate radiation under novel heating conditions and to find the best-fit temperature and material parameters given thermal images. The method is verified using both synthetic and real capture datasets.

Test application at reduced power supply voltage (low-voltage testing) or reduced temperature (low-temperature testing) can improve the defect coverage of a test set, particularly of resistive short defects. Using a probabilistic model of two-line nonfeedback short defects, we quantify the coverage impact of low-voltage and low-temperature testing for different voltages and temperatures. Effects of statistical process variations are not considered in the model. When quantifying the coverage increase, we differentiate between defects missed by the test set at nominal conditions and undetectable defects (flaws) detected at non nominal conditions. In our analysis, the performance degradation of the device caused by lower power supply voltage is accounted for. Furthermore, we describe a situation in which defects detected by conventional testing are missed by low-voltage testing and quantify the resulting coverage loss. Experimental results suggest that test quality is improved even if no cost increase is allowed. If multiple test applications are acceptable, a combination of low voltage and low temperature turns out to provide the best coverage of both hard defects and flaws.

A procedure for using fault dominance in a large volume diagnosis environment is described. Fault dominance is shown to be useful for reducing the fault simulation time during diagnosis when used together with the concept of pattern dependence and maximally dominating faults. Results for both ISCAS benchmarks and industrial circuits are reported. The results show 9 % to 44% average reduction in the fault simulation time for these circuits

We propose techniques to speed up diagnostic fault simulation for circuits without full-scan which may need multi-cycle tests. First, we introduce the concept of z-sets for circuits without full scan and show how z-sets can be used in a preprocessing step to improve the performance of diagnostic fault simulation. Further, an implementation of an equivalence identification tool that executes concurrently with diagnostic fault simulation is described along with methods to increase its efficiency by prioritizing fault pair selection and reducing interprocess communication. Finally, a combination of both these techniques is analyzed and the performance benefit is presented. Experimental results on ISCAS'89 benchmarks and industrial circuits indicate that diagnostic fault simulation is substantially faster by 20.6 to 46.9% when z-sets are used along with concurrent equivalent fault identification

We describe a test generation procedure for path-oriented transition faults that takes into account the fact that operating conditions may change during circuit operation. A path-oriented transition fault is detected through the longest sensitizable path that goes through the fault site. The operating conditions we consider are junction temperature and power supply voltage. Since path delays change with operating conditions, the longest path through a fault site may be different under different conditions. We show that test generation using nominal delays is not sufficient for covering the complete range of operating conditions, even if N-detection test generation is used. Therefore, operating conditions need to be addressed explicitly during test generation. However, since temperature and voltage are continuous variables and represent an infinite number of values in the range, test generation must concentrate on a small selected set of operating conditions. We discuss the selection of these conditions and demonstrate that N-detection test generation with multiple operating conditions is effective in covering the range of operation conditions almost completely.

We define the concepts of z-sets and z-detections for combinational circuits (or the combinational logic of scan circuits). Based on these concepts we define structural characteristics and characteristics based on fault simulation. We show that these characteristics determine the numbers of fault pairs that are guaranteed to be distinguished by a given fault detection test set. These fault pairs do not need to be considered during diagnostic fault simulation or test generation. We demonstrate that benchmark circuits as well as industrial circuits have these characteristics to a larger extent than may be expected. As a result, only small percentages of fault pairs need to be considered during diagnostic fault simulation or test generation once a fault detection test set is available. In addition, these fault pairs can be identified efficiently.

Test application at reduced power supply voltage (or VLV testing) is a cost-effective way to increase the defect coverage of a test set. Resistive short defects are a major contributor to this coverage increase. Using a probabilistic model of these defects, we quantify the coverage impact of VLV testing for different voltages. When considering the coverage increase, we differentiate between defects missed by the test set at nominal voltage and undetectable defects (flaws) detected by VLV testing. In our analysis, the performance degradation of the device caused by lower power supply voltage is accounted for. Furthermore, we describe a situation in which defects detected by conventional testing are missed by VLV testing and quantify the resulting coverage loss. We report the numbers on the increased defect coverage, flaw coverage, and coverage loss for ISCAS circuits.