V. K. Agrawal

dblp:32/4964 · DBLP profile ↗
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6ranked-venue papers
0as first author
0since 2021 · last 2007
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Databases, data management, data science and information retrieval · 2Artificial intelligence and machine learning · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 100% Performance modeling and evaluation · 0%
Theoretical computer science
1 paper
Automata and formal languages · 50% Graph algorithms and graph theory · 50%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › analog and mixed-signal test
analog circuit test generation
0.122007
A New ATPG Technique (ExpoTan) for Testing Analog Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007
A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004
Electronic design automation
hardware test
0.122007
A New ATPG Technique (ExpoTan) for Testing Analog Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007
A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004
Electronic design automation › hardware verification and test
test compaction
0.112007
A New ATPG Technique (ExpoTan) for Testing Analog Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007
Electronic design automation › hardware verification and test › design for testability
built-in self-test
0.012004
A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004
Graph algorithms and graph theory › graph theory › algebraic graph theory
incidence matrices
0.011987
Reflexive Incidence Matrix (RIM) Representation of Petri Nets · IEEE Trans. Software Eng. 1987
Automata and formal languages
petri nets
0.011987
Reflexive Incidence Matrix (RIM) Representation of Petri Nets · IEEE Trans. Software Eng. 1987
Performance modeling and evaluation
asynchronous concurrent systems
0.011987
Reflexive Incidence Matrix (RIM) Representation of Petri Nets · IEEE Trans. Software Eng. 1987

Methods — techniques the papers use, named apart from their topics

test signal identification · 0.1fault coverage optimization · 0.1test set compaction · 0.0frequency-domain testing · 0.0fault simulation · 0.0matrix decomposition · 0.0graph representation · 0.0
YearPublicationVenuePosition
2007 A New ATPG Technique (ExpoTan) for Testing Analog Circuits
abstract
In analog testing, usage of a single sinusoid as a test signal when compared to multitone signal, and fault detection with digital counting technique, facilitate the test implementation with simple built-in self-test hardware and make testing more cost effective. In this paper, a novel test-set-selection technique known as ExpoTan for testing linear-time-invariant (LTI) circuits is presented. The authors formulate the test generation problem with tan-1( ) and exponential functions for identification of a test signal with maximum fault coverage. For identification of a test signal the ExpoTan technique combines test generation and test-set-compaction tasks in a single phase and generates an efficient compacted test set. The experimental results show that the testing of LTI circuits using ExpoTan technique for the benchmark circuits achieves the required fault coverage with shorter testing time and test generation time
B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4
2004 A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits
abstract
A new test-set selection technique based on the frequency-domain testing of analog circuits is presented in this paper. We propose a new automatic test pattern generation (ATPG) method known as MultiDetect for testing linear time invariant (LTI) circuits. The proposed technique is best suited for use of existing building blocks in systems-on-chip for implementation of an on-chip test-signal generator and test-response analyzer. The generated test set with the MultiDetect method can effectively detect and diagnose both soft and hard faults and does not require any precision analog signal sources or signal measurement circuits when implemented as built-in self-test (BIST). Testing of analog blocks based on circuit-transfer function makes our ATPG a general purpose method for all kinds of LTI circuits. A new novel test method causing the device under test to saturate or get out of saturation, to detect a fault with simple detection hardware, is also introduced in this paper. In our proposed novel test scheme, usage of a single sinusoid as a test signal when compared to multitone signal, and detection of faults with digital counting technique, facilitate the test implementation with simple BIST hardware and make testing more cost effective. The sinusoid is a very useful waveform for testing and analyzing LTI circuits. In the steady state, both the input and output of a stable LTI circuit are sinusoids of the same frequency. The relationship between the amplitudes and phase angles of the input and output sinusoids is frequency-dependent. Identification of a sinusoid that detects more faults results in an optimized test signal set. The technique used in the MultiDetect method for identification of a sinusoid results in an efficient compacted test set. The search for fault diagnosis is restricted to a limited set of faults, making diagnosis fast in the MultiDetect method. A methodology for test-set compaction of the MultiDetect technique is described and results of experiments on various test circuits are discussed. The proposed method is seen to be efficient for low-power applications. The experimental results show that the testing of LTI circuits using the MultiDetect technique for the benchmark circuits achieves the required fault coverage with much shorter testing time.
B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4
2001 Genetic programming based pattern classification with feature space partitioning
Lalit M. Patnaik, V. K. Agrawal
Inf. Sci.4
2000 Application of genetic programming for multicategory pattern classification
abstract
Explores the feasibility of applying genetic programming (GP) to multicategory pattern classification problem. GP can discover relationships and express them mathematically. GP-based techniques have an advantage over statistical methods because they are distribution-free, i.e., no prior knowledge is needed about the statistical distribution of the data. GP also automatically discovers the discriminant features for a class. GP has been applied for two-category classification. A methodology for GP-based n-class classification is developed. The problem is modeled as n two-class problems, and a genetic programming classifier expression (GPCE) is evolved as a discriminant function for each class. The GPCE is trained to recognize samples belonging to its own class and reject others. A strength of association (SA) measure is computed for each GPCE to indicate the degree to which it can recognize samples of its own class. SA is used for uniquely assigning a class to an input feature vector. Heuristic rules are used to prevent a GPCE with a higher SA from swamping one with a lower SA. Experimental results are presented to demonstrate the applicability of GP for multicategory classification, and they are found to be satisfactory. We also discuss the various issues that arise in our approach to GP-based classification, such as the creation of training sets, the role of incremental learning, and the choice of function set in the evolution of GPCE, as well as conflict resolution for uniquely assigning a class.
Lalit M. Patnaik, V. K. Agrawal
IEEE Trans. Evol. Comput.4
1991 Extended colored Petri net: An efficient tool for analyzing concurrent systems
Sajal K. Das 0001, Dilip Sarkar, V. K. Agrawal, Lalit M. Patnaik
Inf. Sci.3
1987 Reflexive Incidence Matrix (RIM) Representation of Petri Nets
abstract
Although incidence matrix representation has been used to analyze the Petri net based models of a system, it has the limitation that it does not preserve reflexive properties (i.e., the presence of self-loops) of Petri nets. But in many practical applications self-loops play very important roles. This paper proposes a new representation scheme for general Petri nets. This scheme defines a matrix called "reflexive incidence matrix (RIM) Cr," which is a combination of two matrices, a "base matrix Cb," and a "power matrix Cp." This scheme preserves the reflexive and other properties of the Petri nets. Through a detailed analysis it is shown that the proposed scheme requires less memory space and less processing time for answering commonly encountered net queries compared to other schemes. Algorithms to generate the RIM from the given net description and to decompose RIM into input and output function matrices are also given. The proposed Petri net representation scheme is very useful to model and analyze the systems having shared resources, chemical processes, network protocols, etc., and to evaluate the performance of asynchronous concurrent systems.
Sajal K. Das 0001, V. K. Agrawal, Dilip Sarkar, Lalit M. Patnaik, Prem Shankar Goel
IEEE Trans. Software Eng.2