Peripheral nervous system (PNS) recording plays an essential role in the development of neural-controlled prosthetics. Compared to cortical recording, PNS requires front-end circuitry with lower input-referred noise and higher accuracy. A chopper-stabilized front-end with its transfer function set by precision capacitor ratios that meets these goals is introduced. Using a windowed integration sampling technique, the continuous-time anti-aliasing filter that usually precedes the lowpass switched-capacitor (SC) filter can be eliminated. High gain accuracy is achieved using a closed-loop switched-capacitor topology wherein a chopper-modulatedsincfunction is realized. The corner frequencies of the front-end are determined by a downstream switched-capacitor filter and a DC servo-loop-based SC integrator. The overall energy efficiency is further improved using correlated level shifting in the SC filter and integrator stages to simplify the operational amplifier topology. A positive feedback loop is also incorporated to increase the input impedance. The PNS front-end implemented in 180 nm CMOS has a gain of 58.1 dB and an integrated input-referred noise of$2.2\mu \text{V}_{\mathrm {rms}}$over the -3 dB bandwidth from 170 Hz - 9.68 kHz; the input impedance is$>$61M$\Omega $@ 1 kHz. The total harmonic distortion is -66.6 dB with a 1.8Vppoutput swing. The complete front-end including clock generation circuitry occupies 0.136 mm2, draws$16.1 \mu \text{A}$from a 1.8 V supply, and achieves a noise efficiency factor of 3.5.

Compressed sensing (CS) exploits signal sparsity in some domain to enable sub-Nyquist sampling which increases the energy efficiency of analog-to-digital conversion (ADC) and downstream data processing circuits–the sampling frequency is determined by the information rate, not the usual Nyquist rate. CS techniques for wireless multi-channel bio-signal recording applications based on sigma-delta modulation (SDM) are detailed and used to validate a multi-channel recovery algorithm. The SDM topology allows the required dot product calculations between the measurement and signal vectors to be performed in conjunction with its inherent integration using minimal additional circuitry. It eliminates opamp output saturation concerns and benefits directly from still ongoing Moore’s Law CMOS technology scaling. Finally, a sparse sensing matrix and recovery algorithm are described that exploit similar sparse signatures across multiple channels to improve both signal recovery accuracy and chip area efficiency. Simulation results validate the concepts.

Compressed sensing (CS) is a sampling scheme that exploits signal sparsity to reduce the digitizing rate and thus improve analog-to-digital converter (ADC) power efficiency. By decoupling the analog signal frequency and digitizing rate, the ADC sampling rate is determined by the information rate rather than the maximum signal frequency. Herein we propose a compressed sensing scheme for multi-channel bio-signal recording based on sigma-delta modulation (SDM). The dot products between the signal and measuring vectors are realized by the inherent integration of the SDM with relieved saturation concern. Compared to other CS scheme, front-end based on CS SDM scales better with continuing advances in CMOS technology. A sparse sensing matrix and modified recovery algorithm that exploits similar sparse signatures across multiple channels improve both chip area efficiency and signal recovery accuracy. Detailed analyses are validated by extensive simulation results.

The gm/ID-based design of analog integrated circuits introduced by Silveira, et al. in 1996 [1] employs an empirical transistor sizing methodology using SPICE-generated lookup tables. In the design of ultra-low-power amplifiers, the iconic plots of gm/IDvs VOVsuggest that some devices should be operated deep in weak inversion (e.g., VOV≃ −0.2V) where gm/ID is near maximum. Performance parameters such as gain, bandwidth, thermal noise, power dissipation, etc., benefit from this choice. However, in applications where small-signal settling time is critical (e.g., precision switched-capacitor circuits), the unity-gain phase margin, PM, is a parameter of paramount importance. PM (i.e., small-signal settling time) vs. VOV(i.e., strong, moderate or weak inversion) design considerations are presented in this paper. The key result is that as the design choice of VOVmoves the region of operation from strong to moderate to weak inversion, PM is reduced substantially and settling time is increased dramatically. In addition to new design insights, area-efficient device layout techniques are illustrated that improve performance.