Dynamic Partially Reconfiguration (DPR) on FPGA has attracted significant research interest in recent years since it provides benefits such as reduced area and flexible functionality. However, due to the lack of supporting synthesis tools in the current DPR design flow, leveraging benefits from DPR requires specific design expertise with laborious manual design effort. Considering the complicated concurrency relations among various functions, it is challenging to select appropriate Partial Reconfiguration Modules (PR Modules) and cluster them into proper groups with a proper reconfiguration schedule so that the hardware modules can be swapped in and out correctly during the run time. Furthermore, the design of PR Modules also impacts reconfiguration latency and resource utilization greatly. In this paper, we propose a Maximum-Weight Independent Set model to formulate the PR Module selection and clustering problem so that the original manual exploration can be solved efficiently and automatically. We also propose a step-wise adjustment configuration prefetching strategy incorporated in our model to generate optimized reconfiguration schedules. Our proposed approach not only supports various design constraints but also can consider multiple objectives such as area and reconfiguration delay. Experimental results show that our approach can optimize resource utilization and reduce reconfiguration delay with good scalability. Especially, the implementation of the real design case shows that our approach can be embedded in Xilinx's DPR design flow successfully.

The application specific instruction-set processor (ASIP) offers better computing performance and efficiency by exploiting a set of specific custom instructions (CI) in the processor. However, traditional approaches suffer from the problem that it costs so much computational resource to enumerate and select the optimal custom instructions. In this paper, instead of generating the custom instructions by enumerating all sub-graphs in the data flow graph, we propose a novel custom instruction generation algorithm based on analyzing the basic blocks (BB) which are the smallest execution units of the program. On the basis of characterizing the logic information and structure of basic blocks, both the identification and selection processes could be more efficient by focusing on the feasible candidates with better benefits. A Maximal Weight Independent Set-based formulation is set up to select the final custom instructions based on the efficient identification of candidate custom instructions with logic information of BBs. The experimental result shows that our algorithm can identify 55% more feasible CIs compared with the previous approach. With efficient identification process, we can finally get better CI designs with about 3.27X performance gain of the whole system.

Control and Data Flow Graph (CDFG) is a universal description of program behavior, which is widely used in the co-design of software and hardware. The derivation of CDFG has been done mostly by manually or automatically analyzing corresponding source code, which makes this process time-consuming, error-prone and incomplete. In this paper, we proposed an automated design flow based on runtime instrumentation to generate Enhanced CDFG (ECDFG) with additional runtime information. Though the approach of runtime instrumentation is widely used in software debugging to analyze the program with the accurate runtime information, it is rarely used in software and hardware co-design due to the huge trace data and processing overhead. To overcome the bottle neck of the runtime instrumentation approach, Parallel Background Event Logger is proposed to compress and save the huge amount of trace data. Hierarchical loop structures are detected by intersecting reachable set and backward reachable set. Precise data dependency information is deducted by an address based analytical method named Shower Line Algorithm. With these algorithms and techniques, a set of automatic design tools are implemented to collect runtime events, identify nested and implicit loops and deduct data dependance between modules. Exemplar results demonstrated that Enhanced CDFGs for various programs can be generated correctly with acceptable overhead.

The continuous growth in both capability and capacity for FPGA now requires significant resources invested in the hardware design, which results in two classes of main security issues: 1) the unauthorized use and piracy attacks including cloning, reverse engineering, tampering etc. 2) the licensing issue. Binding hardware IPs (HW-IPs) to specific FPGA devices can efficiently resolve these problems. However, previous binding techniques are all based on encryption and hence have three main drawbacks: 1) encryption-based proposals in commercial are limited to protect the single large FPGA configuration, 2) many encryption-based proposals depend on a trusted third party to involve the licensing protocol, and 3) the encryption-based binding methods use costly mechanisms such as secure ROM or flash memory to store FPGA specific cryptographic keys, which is not only expensive but also vulnerable to side-channel attacks, and the management and transport of secret keys became a practical issue. In this work, we propose a PUF-FSM binding technique completely different from the traditional encryption-based methods to address these shortcomings.

In this paper we propose a novel binding mechanism that can protect FPGA IP from being cloned, tampered, or misused; and facilitate the pay-per-use licensing to limit the FPGA IP's execution to specific FPGA devices only. In this mechanism, the FPGA vendors will provide each enrolled device with a Physical Unclonable Function (PUF) that can be deployed securely during fabrication process. The core vendor will embed an augmented Finite State Machine (FSM) into the original FSM structure of the hardware IP (HW-IP) to react on the PUF response to a given challenge. The proposed binding method does not need any Trusted Third Party (TTP) or block cipher for key management and exchange. We analyze several known attacks to hardware IP and show that our method is secure against these attacks. Experimental results on MCNC benchmarks show that the proposed method incurs small design overhead in terms of area, power and delay.

Dynamic Partial Reconfiguration (DPR) on FPGAs has attracted significant research interests in recent years since it provides benefits such as reduced area and flexible functionality. However, due to the lack of supporting synthesis tools in current DPR design flow, leveraging these benefits requires specific designer expertise with laborious manual design effort. Considering the complicated concurrency relations among functions, it is challenging to properly select Partial Reconfiguration Modules (PR Modules) and partition them into groups so that the hardware modules can be swapped in and out during the run time. What's more, the design of PR Modules also impacts reconfiguration latency and resource utilization greatly. In this paper, we formulate the PR Module generation problem into a standard Maximum-Weight Independent Set Problem (MWISP) so that the original manual exploration can be solved optimally and automatically. Our proposed algorithm not only supports various design constraints, but also has the ability to consider multiple objectives such as area and reconfiguration delay. Experimental results show that our approach can optimize resource utilization and reduce reconfiguration delay with good scalability. Especially, the implementation of the real design case shows that our approach can be embedded in the Xilinx's DPR design flow successfully and it can save around 70% reconfiguration latency overhead compared with the heuristic PR Module generation approaches.

Task scheduling and core mapping have a significant impact on the overall performance of network on chip (NOC). In this paper, a unified task scheduling and core mapping algorithm called UNISM is proposed for different NOC architectures including regular mesh, irregular mesh and custom networks. First, a unified model combining scheduling and mapping is introduced using mixed integer linear programming (MILP). Then, a novel graph model is proposed to consider the network irregularity and estimate communication energy and latency, since the number of network hops is not accurate enough for irregular mesh and custom networks. To make the MILP-based UNISM scalable, a heuristic is employed to speed up our method. Compared with two previous state-of-the-art works, experimental results show that more than 15% and 11.5% improvement on the execution time is achieved with similar energy consumption on average for regular mesh NOC. For irregular and custom NOC, the improvement is 27.3% and 14.5% on the execution time with 24.3% and 18.5% lower energy. Moreover, our method is scalable for large benchmarks in terms of runtime.

To improve the observability in the post-silicon validation, how to select the limited trace signals effectively for the data acquisition is the focus. This paper proposes an automated trace signal selection algorithm, which uses the pruning-based strategy to reduce the exploration space. The experiments indicate that the proposed algorithm can bring higher restoration ratios, and it is more effective compared to existing methods.

To reduce the huge search space when customizing instruction-level accelerators for the application specific instruction-set processor (ASIP), this paper proposes an automated instruction-level hardware/software partition method based on the data flow graph exploration. This method integrates the instruction identification and selection using an iterative improvement strategy. The search space is reduced via considering the performance factors during the identification.

Traditional sequence based routing algorithms for FPGAs usually route only one net at a time, so as to simplify the routing problems. However, with the number of logic blocks in the FPGAs becomes larger and larger, the time need to route each net can increase significantly. A new recursive detailed routing algorithm is proposed to address this problem. As decided by its recursive nature, this algorithm can only be applied for hierarchical FPGAs, which of the architectural features with its connection patterns is also presented in detail in this paper. The overall algorithm begins its routing from the topmost cluster and continues to route for each cluster from top down recursively, where the routing clusters map to the architectural cluster exactly. At each cluster level, a new heuristic is proposed to solve the specific routing problem. The scale of the problem is so small that the heuristic can be considered deterministic and quickly to solve. The proposed algorithm also takes advantages of the architectural features such as the connection patterns of switch box. As a result, the proposed algorithm is very fast in runtime due to all these facts. The experimental results show that detailed routing for a very large circuit can be done very quickly in just a few seconds.

Boolean Satisfiability (SAT) has successfully been applied to the FPGA routing. It has many advantages over the conventional one-net-a-time routing algorithm such as routing all nets concurrently, higher flexibility and unroutability provable. However it also has the limits of scalability and is time-consuming. This paper presents some optimizations to the SAT-based routing approach by applying some architecture related features to the generated the Boolean constraints function. Specifically, Switch Box based connectivity optimization to reduce the variable number for each net, Logic Block pins rearrangement to improve the flexibility for each net and Exclusivity constraints optimization based on net-to-track distribution. Each of the optimizations is discussed in detail in this paper. Some heuristics and algorithms are also presented to implement the optimizations. We implement the SAT-based routing strategy as well as the optimizations on a general hierarchical FPGA architecture. The experimental results show that we can greatly reduce the variable and constraint number of the generated Boolean SAT functions. Hence, the generated SAT functions can be solved much more quickly. It also shows that high routing flexibility is also achieved due to the pins rearrangement.

Dual-Vthdesign is an effective leakage power reduction technique at behavioral synthesis level. It allows designers to replace modules on non-critical path with the high-Vthimplementation. However, the existing constructive algorithms fail to find the optimal solution due to the complexity of the problem and do not consider the on-chip temperature variation. In this paper, we propose a two-stage thermal-dependent leakage power minimization algorithm by using dual-Vthlibrary during behavioral synthesis. In the first stage, we quantitatively evaluate the timing impact on other modules caused by replacing certain modules with high Vth. Based on this analysis and the characteristics of the dual-Vthmodule library, we generate a small set of candidate solutions for the module replacement. Then in the second stage, we obtain the on-chip thermal information from thermal-aware floorplanning and thermal analysis to select the final solution from the candidate set. Experimental results show an average of 17.8% saving in leakage power consumption and a slightly shorter runtime compared to the best known work. In most cases, our algorithm can actually find the optimal solutions obtained from a complete solution space exploration.

As a global interconnection, bus is critical for chip performance in deep submicron technology. Reducing bus routing vias will facilitate the lithography and give bus routing a higher yield and also a higher performance. In this paper, we present a floorplan revising method to minimize the number of reducible routing vias with a controllable loss on the chip area and wirelength. Therefore, it is easy to make a proper tradeoff between via reduction and revising loss. Experiments show that our method reaches a 96.2% and 93.5% reduction of routing vias, which is close to 100% and runs fast. Besides, our revising is friendly to all third-party floorplanners, which can be applied to any existing floorplans to reduce vias. It is also scalable to larger benchmarks.

In this paper, a wirelength-driven force-directed three-dimension (3-D) Field Programmable Gate Arrays (FPGA) placement algorithm (3D-WFP) is presented. The algorithm is composed of three stages: Overlap permitted force-directed 2-D placement, legalization and 3-D layer partition. Different from traditional partition-based 3-D placers, we adjust the layer partition process after the 2-D global placement, which effectively provides the global interconnection and timing information for the next two sub-steps. To legalize the position of the logic block, a 3-D space filling curve is adopted. A low temperature simulated annealing (SA) is used to determine the blocks final layer. Only blocks with the same horizontal coordinate are permitted to interchange, the speed of the SA is very fast. Compared to recently publish 3-D FPGA placement work, this algorithm improves the half perimeter wire-length (HPWL) by 8.57%, almost at the same time cost and keeps the same timing performance.

We propose the use of mutation-based error injection to guide the generation of high-quality diagnostic test patterns. A software-based fault localization technique is employed to derive a ranked candidate list of suspect statements. Experimental results for a set of Verilog designs demonstrate that a finer diagnostic resolution can be achieved by patterns generated by the proposed method.

Constrained random stimulus generation plays significant roles in hardware verification nowadays, and the quality of the generated stimuli is key to the efficiency of the test process. In this work, we present a linear dynamic method to guide random stimulus generation by SAT solvers. A splitting simplified Min-Distance-Sum evaluation method and an XOR sampling strategy are integrated in the self-adjusting random stimulus generation framework. The evenness of the split groups is evaluated to find out some uneven parts. Then, random partial solutions for the uneven parts and random XOR constraints for the other inputs are added into constraints to get better distributed stimuli. Experimental results show that our method can evaluate the evenness as well as more complex formulae for stimulus generation, and also confirm that the self-adjusting method can improve the fault coverage ratio by more than 17% averagely with the same number of stimuli.

High temperature adversely impacts on reliability, performance, and leakage power of ICs. In behavioral synthesis, both resource usage allocation and resource binding influence the final thermal profile. Previous thermal-aware behavioral syntheses only focused on binding, ignoring allocation. This paper proposes thermal-aware behavioral synthesis with resource usage allocation. According to power density and feedbacks from thermal simulation, we allocate the number of resources under area constraint. Our flow effectively controls peak temperature and creates even power densities among resources of “different” and “same” types. Compared to classic behavioral synthesis of peak temperature control, our technique reduces peak temperature by 11.1 °C on average with no area overhead and only 1.2 more steps latency overhead.

The detailed timing information obtained from design iteration can only be added into synthesis process manually. A new strategy for automatic synthesis of backing marked timing information is presented in this paper. As the carrier of backing marked timing information, the delay statements in VHDL is synthesized in scheduling process. And a new scheduling algorithm is presented in this paper. The delay statements are considered to be delay time constraints by the algorithm. Scheduling data structure: DTC_DFG(delay time constrained data flow graph) is constructed and scheduled. A heuristic method is presented in this paper for the scheduling algorithm to jump out local optimization and reach global optimization under polynomial timing complexity. Experimental results are also presented in this paper. With the synthesis of delay statements, the backing marked timing information can be synthesized automatically, and the behavioral timing in design source can be synthesized directly, thus the timing consistency between synthesis result and simulation result can be improved. The delay statements then can be a convenient means to set timing constraints, thus the manual interruption in synthesis process can be decreased; the design efficiency can be improved greatly.

In this paper, we propose a fast placer for FPGA placement on a new commercial hierarchical FPGA device. The novelty of this research lies in the application of a multilevel V-shape optimization flow including an architecture related cluster process and a constructive placement. The new placer can handle large-scale FPGA placement problem quickly. Experimental results show that the proposed placer can further reduced the wirelength average 28.3% compared with simulated annealing based tool while achieving near 5X speedup in runtime for the five largest MCNC benchmarks.

Cell migration has been widely used in global placement for the highly efficiency in smoothing cells overlap. The current cell migration methods only locally or globally smooth the density without considering the relation between the local and the global density. Furthermore, the cells generally are treated as points with area. In this paper we present a new cell migration technique called CSAGO to even the overlap. CSAGO obtains the movement distance while considering the local and the global density distribution simultaneously. By separating the standard cells and the macro blocks crossing multi-bin, a more smooth migration speed can be obtained. CSAGO has been embedded into the global placement process, experimental result shows that average HPWL have reduced 3% and the total runtime is 1.78 times faster than DPlace.

Constrained random simulation methodology still plays an important role in hardware verification due to the limited scalability of formal verification, especially for the large and complex design in industry. There are two aspects to measure the stimulus generator which are the quality of the stimulus generated and the efficiency of the generator. In this paper, we propose a self-tuning method to guide the generation for constrained random simulation by SAT solvers. We use a greedy search strategy in solving process to get the high-uniform distribution of the stimulus, and improve the efficiency of the generator by affinity grouping. Experimental results show that our methods can generate more uniform random stimulus with good performance.

Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buffers for robustness against variations. That is, clock buffers are often placed far from ideal locations to avoid overlap with logic cells. As a result, both power dissipation and timing are degraded. In order to solve this problem, we propose a low power clock buffer planning methodology which is integrated with cell placement. A Bin- Divided Grouping algorithm is developed to construct virtual buffer tree, which can explicitly model the clock buffers in placement. The virtual buffer tree is dynamically updated during the placement to reflect the changes of latch locations. To reduce power dissipation, latch clumping is incorporated with the clock buffer planning. The experimental results show that our method can reduce clock power significantly by 21% on average.

To reduce the miss rate of the instruction cache, a hardware-assisted loop optimization method is proposed in this paper. This method utilizes the hardware/software co-design strategy on the behavior level. Especially, this method is equipped with the specific instruction set to limit the cache misses, which can be viewed as a set of hardware for special purposes. Then based on the specific instruction set, a scheduling process is integrated which reduces the cache miss rate through the code transformation. Finally, a set of benchmarks from MediaBench1.0 are tested on the SimpleScalar platform to assist the proposed method. The final experiments indicate that 26% enhancement can be obtained for the cache miss reduction, where the specific instruction generation and the scheduling processes contribute about 23% and 3% respectively.

Recent generation of FPGA devices takes advantage of speed and density benefits resulted from heterogeneous FPGA architecture, in which several basic LUTs can be combined to form one larger size LUT called Macro. Large Macros not only decrease network depth efficiently but also reduce area. In this paper, a new technology mapping algorithm, named MacroMap is proposed for the heterogeneous FPGAs with effective area estimation to overcome the main disadvantage that traditional technology mapping algorithms only generate one kind of typical K-LUT and cannot make full use of LUTs with different sizes (basic LUTs and Macros). Experimental results show that MacroMap can obtain 19% gain on area while keeping the network depth optimal compared with the existing heterogeneous FPGA mapping algorithm heteromap[8].

This paper presents an efficient hybrid memory access optimization system called HyMacs, which integrates the hardware and software optimization strategies in the embedded system design. First, HyMacs features a pre-configuration stage which is equipped with a memory configuration algorithm to satisfy area constraints. Then a custom instruction generation process is integrated in the system via a seed-growth algorithm under the intelligent guide functions. The custom instruction benefits to the reduction of the whole memory access latency and thus relieves the burden of system through hardware mode. Finally, a data-dependency-driven scheduling algorithm is also integrated to compress the whole latency through access mode conversion. We have tested the system on a set of commonly used benchmarks, and compared the results with the previous memory access system MACCESS-opt proposed in DAC'05. The experimental results indicate 20% enhancement obtained for the total memory access latency reduction compared with MACCESS-opt, where the custom instruction generation and scheduling contribute about 15% and 5% respectively.

Fixed-outline floorplanning, which enables hierarchical design, is considered more and more important nowadays. In this paper, a novel SA-based Fixed-outline Floorplanner with the Optimal Area utilization named SAFFOA is introduced to improve the total wirelength. The basic idea is to build and solve a group of four quadratic equations in four variables iteratively, which can handle the fixed-outline constraint of any aspect ratio. A new topological representation called Ordered Quadtree is then custom-made for this basic idea to facilitate its integration into SA iterations. After the fixed-outline constraint with 100% area utilization is achieved, we will solve the tradeoff between the chip area and wirelength and thus concentrate on the latter in SA process. Experimental results show that the chip wirelength is decreased by about 16.8% and 8.6% on average, compared with two previous fixed-outline floorplanners on soft modules, which are both proved to be better than Parquet. Besides, our method is still competitive on the wirelength, even if compared with some leading-edge outline-free floorplanners. At last, Local Refinement is also adopted to guide the SA process and reshape soft modules to meet the constraint on their aspect ratios (ARs). With its help, SAFFOA can still generate feasible floorplans with no deadspace under a strict AR constraint such as [0.5,2].

This paper presents a new method to translate Verilog HDT into RTL Model combining algorithm description for high level verification. The model could be used in the enhanced version of a state-of-the-art finite-domain satisfiability (SAT) solver EHSAT to check the verified properties. The enhanced version of EHSAT provides an efficient algorithm to solve the SAT problem for higher level abstraction RTL designs using a hybrid branch-and-bound strategy with conflict-driven learning. This modeling program analyses the control flow of Verilog source codes and generates corresponding statements for the enhanced version EHSAT. This method could largely reduce the scale of model checking and simplify the devices used in EHSAT. Experimental results show that this method can reduce verification problem sizes considerably while comparing with lower level methods.

Compared with traditional fixed Instruction set architecture (ISA) processor, configurable processors can reduce the total number of execution cycles dramatically because the instruction set customization permits a much closer fit of the processor to target application. At the same time, custom instruction can also improve the energy efficiency remarkably. However, ISA customization does not always bring power efficiency Instead, sometimes it even increase the power consumption. To address this issue, this paper distinguishes energy efficiency from power efficiency via time granularity. Furthermore, a method combining ISA customization with frequency and voltage scaling is proposed to achieve both favorable energy and power efficiency.

VPH (versatile placer for hierarchical FPGAs, HFPGAs) is a place tool aiming at a routability-driven placement process for HFPGAs. It improves the placement algorithm of VPR (versatile place and route) by taking into consideration of specific constraints of hierarchical architectures for HFPGAs, and updates the place process based on it. Further more, thanks to the interconnect predictability, VPH can take into account routing constraints in early placement stage and evaluate efficiently the routability of the circuit. In this paper, we introduce the VPH design framework and its related placement algorithms. Its effectiveness is validated by the experimental results of MCNC benchmark.

In this paper, we present management system of metropolis energy information (MSMEI) that manages the information of water meter, electricity meter and gas meter, the three basic elements of a city. In contrast to the traditional system as "single-user" program for collecting data, we have founded an architecture offering surprisingly strong support for cooperation among different workgroups. CSCW allows different workgroups to collaborate on goals including improving data reliability and accuracy, improving working efficiency, reducing labor cost, etc.

To improve the computation efficiency of application specific instruction-set processor (ASIP), a strategy of hardware/software collaborative design is usually utilized. In this process, the auto-customization of instruction set has always been a key part to support the automated design of ASIP. The key issue of this problem is how to effectively reduce the huge exponential exploration space in the instruction identification process. To address this issue, we first formulate it as a sub-graph enumeration problem under multi-constraints, and then propose a fast instruction identification algorithm based on basic convex pattern (BCP) model. The kernel technique in this algorithm is the transformation from the graph exploration to the formula-based computations. Experimental results have indicated that the proposed algorithm has a distinct reduction on the execution time.

This paper presents an efficient algorithm to solve the satisfiability (SAT) problem for RTL designs using a complete hybrid branch-and-bound strategy with conflict-driven learning. The main framework is the extended Davis-Putnam-Logemann-Loveland procedure (DPLL) which is a unified procedure combining Boolean logic and arithmetic operations. A hybrid two-literal-watching scheme and interval reasoning based on RTL predicates are used as the powerful hybrid constraint propagation strategies. Conflict-based learning is also implemented as another important technique to enhance efficiency. Comparisons with a state-of-the-art RTL SAT solver, a SMT solver and an ILP solver show that EHSAT outperforms these solvers for RTL satisfiability problems.

More and more IP cores are used in modern SOC designing. In order to place IP cores effectively, hierarchical design has been introduced and better supported by fixed-outline floorplanning than outline-free [1]. In this paper, we also consider buffer insertion issue in fixed-outline floorplanning with the help of the Less Flexibility First (LFF) algorithm, which runs in a fixed-outline area and places IP cores as hard modules one after another with no backtracks. Unlike Simulated Annealing (SA), LFF is a deterministic packing algorithm and runs without topological representations. Therefore, it is able to tell the difference among geometric floorplans with the same topological structure, which is helpful to get a better result for buffer planning since buffer insertions are quite sensitive to a geometric change. Moreover, a 2-staged packing and a post greedy method after packing are also introduced based on a net-classing strategy and finally help to achieve great success rate improvement of buffer insertion (about +40.7% in 0.18um and +37.1% in 0.07μm). Meanwhile, our buffer planning method runs much faster than SA, since it is deterministic and has no backtracks. Besides, it is also useful to provide an initial solution for SA for further optimization.

In this paper, we investigate thermal via (T-via) planning during three-dimensional (3-D) floorplanning. First, we consider the temperature constrained T-via planning (TVP) problem on a given 3-D floorplan. Second, we integrate dynamic TVP into 3-D floorplanning process. Our main contribution and results can be summarized as follows. We solve the temperature constrained TVP problem by solving a sequence of simplified interlayer and intralayer TVP subproblems. Each subproblem is formulated as convex programming problem and we derive nearly optimal solution for detailed T-via distribution. Based on the TVP solution, we implement the integrated TVP and 3-D floorplanning algorithm in a two-stage approach. Before floorplanning, blocks are assigned into different layers by solving a sequence of knapsack problems. During floorplanning, T-vias are allocated with white space redistribution to optimize T-via insertion. Experimental results show that our TVP approach can reduce T-vias by 12% compared with a recent published work (J. Cong and Y. Zhang, "Thermal via planning for 3-D ICs," in Proc. Int. Conf. Comput.-Aided Des., Nov. 2005, pp.745-752). Compared with the postfloorplanning optimization approach, integrating TVP into floorplanning process can reduce T-vias by 16% with 21% runtime overhead

This paper presents a cooperative bounded model checking (BMC) method for RTL designs. The method firstly extends the Boolean DPLL algorithm into a unified procedure to solve hybrid satisfiability problems for RTL circuits, and then changes this solver to a hybrid three-valued SAT solver. Symbolic trajectory evaluation (STE) assertions are transformed to a three-valued problem combining the expansion method in BMC and the abstraction of STE. The experimental results comparing with ordinary BMC which based on an ordinary hybrid SAT solver demonstrate the efficiency of our approach

Communication architecture design is a key issue of hardware/software co-design. This paper presents a novel architecture design method, called architecture generation and optimization method (AGOM) to assist embedded system designers to construct optimized on-chip communication architectures (OOCAs). The method outlines a new system design framework to achieve an application-specification architecture exploration process. Under its guide, chip designers can easily synthesize the desired communication structure by the approach of model refinement from one level of abstraction down to another closer to implementation. To automate the key steps of the method, this paper also provides communication synthesis algorithms of architectures generation and optimization based on a pre-partitioned hardware/software specification. During the architecture exploration process, the approach takes into account bus widths, bus load, cost for arbitration logic and transducers to achieve a fine trade-off between system delay and area. The correctness and effectiveness of the method is evaluated through an illustrative JPEG application

The rapidly increasing complexity of integrated circuit design is evolving to a more data-centric design scenario that supports sharing of design information. This paper presents the concepts of universal data model platform (UDMP) which introduce the data-centric design revolution into the domain of system level design to support better cooperation of individual steps in electronic design automation (EDA) industry. The goal of UDMP is to provide a set of universal data models which enables wide variety of codesign tools to be integrated tightly and revitalizes the connection between universities and the EDA industry. Furthermore, an application programming interface (API) takes the place of traditional low-bandwidth file formats to provide access to the internal data models, thus improves efficiency of design iteration. The well-constructed structure of UDMP brings some challenges for the architects as well as current system level researchers and designers. The concepts of UDMP are applied to a simplified interface synthesis flow which contains three algorithms. Primary experiment results show that these algorithms are simplified with a running time reduction by about 10% for selected designs

Incorporating thermal vias into 3D ICs is a promising way to reduce circuit temperature by lowering down the thermal resistances between device layers. In this paper, we integrate dynamic thermal via planning into 3D floorplanning process. Our 3D floorplanning and thermal via planning approaches are implemented in a two-stage approach. Before floorplanning, the temperature-constrained vertical thermal via planning is formulated as a convex programming problem. Based on the analytical solution, blocks are assigned into different layers by solving a sequence of knapsack problems. Then a SA engine is used to generate floorplans of all these layers simultaneously. During floorplanning, thermal vias are distributed horizontally in each layer with white space redistribution to optimize thermal via insertion. Experimental results show that compared to a recent published result from [14], our method can reduce thermal vias by 15% with 38% runtime overhead.

New three-dimensional (3D) floorplanning and thermal via planning algorithms are proposed for thermal optimization in two-stacked die integration. Our contributions include (1) a two-stage design flow for 3D floorplanning, which scales down the enlarged solution space due to multidevice layer structure; (2) an efficient thermal-driven 3D floorplanning algorithm with power distribution constraints; (3) a thermal via planning algorithm considering congestion minimization. Experiments results show that our approach is nine times faster with better solution quality compared to a recent published result. In addition, the thermal via planning approach is proven to be very efficient to eliminate localized hot spots directly.

Architectural exploration is very important in embedded system design and SoC design. In this paper, a new heuristic algorithm using the allocation-on-demand technique is proposed to solve this problem. Unlike previous research efforts, this algorithm allocates new resources only when it fails to schedule tasks under the performance constraints. So the resource costs of the system increase monotonously in running, which is apt to determine the feasibility of current solution earlier. Experimental results show that this approach is helpful for an efficient architectural exploration process.

In this paper, we present an iTuCoMe methodology which concentrates on providing a brand-new codesign framework of high-performance SoC systems for multilevel exploration. The main motivation of this work is that a fine trade-off between abstraction levels, design models and implementation accuracy can be explored under the design cycle as small as possible at system level. The proposed framework has been realized by relative algorithms and tools to map and transform a system specification to a feasible RTL implementation solution with arbitrarily linked processors, IP cores and ASICs. To improve the speed of convergence and reduce the iterative numbers of turnaround, iTuCoMe employs an incremental method to divide design space into three layers: 1) adaptive granularity for HW/SW partitioning; 2) incremental tuning for communication architecture generation; and 3) interconnect-driven high-level re-synthesis with floorplanning. Finally, we evaluate the iTuCoMe design methodology through an illustrative case study on JPEG decoder application.

For a mixed control and data intensive design, neither model checking nor simulation alone can handle the property-checking problem effectively. Model checking is more suitable for checking the control part and simulation of the data part. In this paper, we propose to let the two techniques cooperate to complete the problem. We choose SMV, a symbolic model checking tool, and Jeda, a hardware verification language for the cooperation work. The work flow of cooperation is described. Experimental results show that by cooperation, the verification is speedup considerably.

This paper is concerned with Boolean satisfiability (SAT) problem. Many researchers are devoted into seeking for new ideas as well as developing more efficient SAT solvers which will improve the development of EDA (electronic design automation). We try to solve the SAT problem by fuzzy genetic algorithm with partitioning-based initial process, namely PFGASAT. Some heuristic mechanisms have been introduced which make the algorithm more intellective. Primary experiments show that PFGASAT can solve SAT problems with more than 15 k variables while behaves rather stably and robustly.

Based on the advantages of simulation and model checking with CDFG structure, classified properties are proposed and defined for simulation, CDFG matching, and model checking respectively. With ITC99 benchmarks, the designed properties are verified, and the experimental results show that different properties should be verified distinguishingly.

Article Free Access Share on IBAW: an implication-tree based alternative-wiring logic transformation algorithm Authors: Wangning Long Dept. Computer Sci. & Tech., Tsinghua University, Beijing, 100084, China Dept. Computer Sci. & Tech., Tsinghua University, Beijing, 100084, ChinaView Profile , Yu-Liang Wu Dept. Computer Sci. & Eng., The Chinese University of HK, Shatin, NT, Hong kong Dept. Computer Sci. & Eng., The Chinese University of HK, Shatin, NT, Hong kongView Profile , Jinian Bian Dept. Computer Sci. & Tech., Tsinghua University, Beijing, 100084, China Dept. Computer Sci. & Tech., Tsinghua University, Beijing, 100084, ChinaView Profile Authors Info & Claims ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation ConferenceJanuary 2000 Pages 415–422https://doi.org/10.1145/368434.368720Online:28 January 2000Publication History 6citation79DownloadsMetricsTotal Citations6Total Downloads79Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

In this paper, we defined a new FSM model based on the synchronous behavior and symbolic representation technique. The algorithm to elaborate the model from the VHDL description of synchronous circuits is presented. By eliminating the unnecessary transition function, our model has much less states than Deharbe's mixed model. The experimental results demonstrate the model and modeling method can make symbolic model checking more practical.

In this paper, a high-level design system called VIDE (Visual VHDL Integrated Design Environment) is presented. In VIDE, there are several graphical and textual mixed design entry tools (VDES=Visual Design Entry System) and a graphical object-oriented debugger (VDBG=Visual DeBuGger). VDES consists of several diagram editors and a visual text editor, while VDBG is a debugging environment based on a hierarchical VHDL simulator. The graphical objects can be specified as a debugging target.