The conversion from a Residue Number System (RNS) to a weighted representation is a costly inter-modulo operation that introduces delay and area overhead to RNS processors, while also increasing power consumption. This paper proposes a new approach to decompose the reverse conversion into operations that can be processed by the arithmetic units already present in the RNS independent channels. This leads to a more effective reuse of the processor circuitry while enhancing parallelism. Experimental results show that, when the proposed techniques are applied to architectures based on ripple-carry adders for the traditional 3-moduli set, the delay is improved in average by 16 percent, the circuit area by 36 percent and the power consumption by 47 percent. When carry-lookahead adder topologies are considered, these improvements are in average of 45 percent for the circuit area and 58 percent for the power consumption while the delay is only slightly reduced. The proposed techniques are applied to a use case in digital filtering, showing an increase in throughput/area of up to 1.25 times, and average reductions in energy consumption of 15.6 percent. This work is a step forward to the usage of RNS in practice, since reverse conversion underpins other hard inter-modulo operations, like comparison, scaling and division.

This paper presents a procedure to optimize modular multiplication by constants. Such operations have been demonstrated to be crucial to design efficient reverse converters, which are the bottleneck of RNS. The focus of this work is the use of Residue Number System (RNS) moduli sets without limitation of the number of channels, which are useful for Digital Signal Processing (DSP) applications. Moreover, an improved hardware architecture for a reverse converter algorithm by using balanced generic moduli sets is presented too. The experimental results show that the optimization of modular multiplication by constant on reverse converters provides a speedup of 1.40 times and average area reduction of 27% for maximum dynamic ranges presented in the state of the art.

In the last years, research on residue number systems (RNS) has targeted larger dynamic ranges in order to further explore the inherent parallelism of these systems. In this paper, a performance analysis is presented for RNS-to-binary architectures based on New Chinese Remainder Theorem I (New CRT-I). Four different approaches are explored, each of them focused on the area or delay reduction of one specific stage of the converter. In addition, a selection of the constants associated to these algorithm approaches is proposed, which results into significant area reductions. Experimental results show that the use of an appropriate parameter selection can achieve a reduction of area and delay around 21% in comparison with the best solutions existing in the state-of-the-art using the New CRT-I technique and conventional parameter selection.

Power analysis attacks are one of the most common Side-Channel Attacks (SCAs), proven to be extremely successful even on protected embedded devices. This paper proposes the use of a Residue Number System (RNS) architecture with randomly permuted moduli sets to implement the Double-and-Add computation, which is proven as the most susceptible operation in Elliptic Curve Cryptography (ECC). The proposed solution randomly permutes the moduli sets, allowing randomized power traces, significantly removing the correlation between the power dissipation and the secret key and eliminating the need for the intermediate conversion to binary required in the state-of-the-art. Architectures obtained for a 90nm standard cell technology suggest that a significant power analysis resistance is achieved for the Double-and-Add circuitry, incurring an extra performance cost of 3 times compared to the related state-of-the-art.

Security in embedded systems is of critical importance since most of our secure transactions are currently made via credit cards or mobile phones. Power analysis based side channel attacks have been proved as the most successful attacks on embedded systems to retrieve secret keys, allowing impersonation and theft. State-of-the-art solutions for such attacks in Elliptic Curve Cryptography (ECC), mostly in software, hinder performance and repeatedly attacked using improved techniques. To protect the ECC from both simple power analysis and differential power analysis, as a hardware solution, we propose to take advantage of the inherent parallelization capability in Multi-modulo Residue Number Systems (RNS) architectures to obfuscate the secure information. Random selection of moduli is proposed to randomly choose the moduli sets for each key bit operation. This solution allows us to prevent power analysis, while still providing all the benefits of RNS. In this paper, we show that Differential Power Analysis is thwarted, as well as correlation analysis.

This paper presents a novel approach to improve the existing Binary-to-RNS multi-moduli architectures. These architectures reduce the complexity by sharing common intermediate results among various RNS moduli channels. Two types of multi-moduli architectures are distinguished depending on whether the functionality is implemented serially or in parallel. A novel choice of the weights associated to the inputs provides huge improvement when applied to the most efficient topology known to date. Experimental results suggest that the proposed memoryless multi-moduli architectures achieve speedups of 2.02 and 1.79 for parallel and serial implementations, respectively, in comparison with the most efficient state-of-the-art structures. Furthermore, such implementations herein proposed have demonstrated that area reductions of 5.02% and 44.02% are achieved for parallel and serial structures, respectively.

Recently new Residue Number Systems (RNS) moduli sets have been proposed in order to increase the dynamic range and reduce the width of channels, therefore, reducing the processing time and further exploiting the carry-free characteristic of the modular arithmetic. In this paper we propose improved units for addition, subtraction, and multiplication in RNS for modulo {2n±k}. With this work, the somewhat disregarded field of RNS unit design is covered, encouraging the development of moduli sets with channels other than the traditional {2n}, {2n±1} modulo. In order to evaluate the performance of the proposed structures, they are compared with the well known units for modulo {2n}, {2n±1}, and {2n±3}. These structures allow to implement generic units for modulo {2n±k}, in the case of modular multiplication it is achieved the same critical path delay and merely 4% of increase on area resources, when compared with the dedicated structure presented in the state-of-art for modulo {2n±3}.

This paper presents a new scheme for designing residue generators using threshold logic. This approach is based on the periodicity of the series of powers of 2 taken modulo 2n± k. In addition, a new algorithm is proposed to obtain a new set of partitions which are more advantageous in terms of area and delay for the presented topology. Experimental results in the analized range of k and n show that new proposed circuits using the novel partitioning are 70% faster and provide area savings of 64%, when compared with similar circuits using the partitioning methods presented to date.

Many logic circuit applications of resonant tunneling diodes are based on the MOnostable-BIstable Logic Element (MOBILE). Threshold logic is a computational model widely used in the design of MOBILE circuits, i.e. these circuits are built from threshold gates. More recently, generalized threshold gates, also suitable to be realized with MOBILE RTD structures, are being investigated. In this paper we propose a novel MOBILE circuit topology obtained by exploiting threshold logic concepts and properties. A comparison in terms of speed and power performance between the proposed topologies and previous reported ones is carried out.

Many logic circuit applications of RTDs are based on the monostable-bistable logic element (MOBILE). Cascaded MOBILE gates are operated in a pipelined fashion using a four phase overlapping clocking scheme. To improve the robustness of MOBILE networks, a simpler clock scheme is desirable. We have demonstrated that removing the return to a "precharge" voltage behaviour of conventional MOBILE gates, operation with a single phase clock scheme is possible. In this paper, a non return MOBILE logic family is described and its single phase operation shown. A comparison between return and non return gates is carried out showing that in addition to the simpler clock scheme required, speed and power-delay product improvements can be achieved with the proposed ones

One of the most attractive features of MOBILE-based circuits is their self-latching operation, which allows pipelining at the gate level, and thus very high through-output, without any area overhead associated to the addition of the latches. However, the self-latching behavior is not inherent to the practical circuit topologies employed to implement MOBILE circuits. This paper reports on very simple MOBILE structures supporting this statement. The analysis performed allows extracting design guidelines to guarantee the required behavior

Threshold logic is a computational model widely used in the design of resonant tunnelling diodes (RTDs) based circuits, i.e. these circuits are built from threshold gates. This paper explores two other computational models, generalized threshold gates (GTG) and multi-threshold threshold gates (MTTGs), also suitable to be realized with mobile based RTD structures. Circuits implementing them are described. Both logic models are generalizations of threshold logic and so the proposed circuit topologies further increase the functionality of the original TGs. Implementations of a non threshold function with the GTG and MTTG topologies are shown and compared.

This work presents novel and extremely compact implementations of programmable gates on the basis of the multi-threshold threshold gate concept. The circuit consists of resonant tunnelling diodes (RTDs) and heterostructure field effect transistors (HFETs) and its operating principle is based on the controlled quenching of clocked series-connected RTDs. The proposed generic circuit topology is presented and the methodology to design specific programmable gates is introduced. A number of programmable gates are shown and their operation is validated.