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Michael Dd. Schuster

dblp:32/5328 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1985
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 83% Performance modeling and evaluation · 17%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
fault simulation
0.011985
Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator · DAC 1985
Electronic design automation
hardware verification and test
0.011985
Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator · DAC 1985
Electronic design automation › hardware verification and test › fault simulation
switch-level fault simulation
0.011985
Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator · DAC 1985
Performance modeling and evaluation › simulation
concurrent simulation
0.011985
Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator · DAC 1985
Performance modeling and evaluation
simulation
0.011985
Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator · DAC 1985

Methods — techniques the papers use, named apart from their topics

switch-level modeling · 0.0fault simulation · 0.0
YearPublicationVenuePosition
1985 Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator
abstract
This paper presents measurements obtained while performing fault simulations of MOS circuits modeled at the switch level.In
Randal E. Bryant, Michael Dd. Schuster
DAC2