In advanced technology nodes, accurate glitch modeling is crucial for designing high-performance, energy-efficient, and reliable integrated circuits. In this work, we present a new approach for gate-level glitch propagation modeling, employing efficient Artificial Neural Networks (ANNs) to accurately estimate glitch shape characteristics, propagation delay, and power consumption. Moreover, we propose an iterative workflow that integrates our models into standard cell libraries, exploiting the available accuracy and size trade-off. Experimental results on gates implemented in 7 nm FinFET technology indicate that our ANNs exhibit a strong correlation with SPICE (R2over 0.99). Therefore, our approach could enable accurate full-chip glitch analysis and effectively guide glitch reduction techniques.

Architectural exploration of novel technological options, such as 3D integration, requires close interaction with physical implementation. However, the lack of information regarding the technical aspects of the 3D flavor, and lack of open source tools are the key obstacles inhibiting the wide use of physicalaware 3D architectural exploration. To palliate this problem, we present 3DPX, an open-source methodology for 3D physical design exploration based on the OpenROAD framework. By leveraging open standards and tools, our methodology enables evaluation of the impact of 3D stacking on performance, power, and area (PPA). Experimental results on a set of RISC-V benchmark circuits show the expected 50% area reduction, while allowing users to analyze and optimize timing and power just as they would in a traditional 2D flow.

Multiple Input Switching (MIS) effects commonly induce undesired glitch pulses at the output of CMOS gates, potentially leading to circuit malfunction and significant power consumption. Thus, accurate and efficient glitch modeling is crucial for the design of high-performance, low-power, and reliable ICs. In this work, we present a new gate-level approach for modeling glitch effects under MIS. Unlike previous studies, we leverage efficient Machine Learning (ML) techniques to accurately estimate the glitch shape characteristics, propagation delay, and power consumption. To this end, we evaluate various ML engines and explore different Artificial Neural Network (ANN) architectures. Moreover, we introduce a seamless workflow to integrate our ANNs into existing standard cell libraries, striking an optimal balance between model size and accuracy in gate-level glitch modeling. Experimental evaluation on gates implemented in 7 nm FinFET technology demonstrates that the proposed models achieve an average error of 2.19% against SPICE simulation while maintaining a minimal memory footprint.

As semiconductor manufacturing technologies progress beyond the current 3nm, the demand for more compact and powerful VLSI circuits obliges on-chip power grid networks to become denser, resulting in a substantial increase in current densities. Consequently, Electromigration (EM) has emerged as a critical reliability concern since it can lead to voids on the metal wires and, consequently, large IR drops. In this paper, we present an EM/IR-aware wire sizing methodology based on the Particle Swarm Optimization (PSO) algorithm. Our methodology can be effectively applied to contemporary power grid networks to achieve the targeted lifetimes of the chip, and simultaneously resize the wires for area reduction. The advantage is that the proposed approach is able to deal with high-dimensional search spaces, which is imperative in our problem. Experimental results using the large-scale industrial IBM power grid benchmarks indicate that our new approach can increase the lifespan of the power grid up to 6.47 × while effectively reducing the area up to 65%.

Abstract Fraud detection and prevention has received a lot of attention from the research community due to its high impact on financial institutions’ revenues and reputation. The increased use of the web and the provision of online services open up the pathway for exposing these systems to numerous threats and jeopardizing their effective functioning. Naturally, financial frauds are increased in number and form imposing various requirements for their efficient and immediate detection. These requirements are related to the performance of the adopted models as well as the timely response of the decision-making mechanism. Machine learning and data mining are two research domains that can provide a number of techniques/algorithms for fraud detection and setup the road for mitigation actions. However, these methods still need to be improved with respect to the detection of unknown fraud patterns and the incorporation of big data processing mechanisms. This paper presents our attempt to build a hybrid system, i.e., a sequential scheme for combining two deep learning models and efficiently detecting potential financial frauds. We elaborate on the combination of an autoencoder and a Long Short-Term Memory Recurrent Neural Network trained upon datasets which are processed through the use of an oversampling technique. Oversampling is adopted to handle heavily imbalanced datasets which is the ‘natural’ scenario due to the limited number of frauds compared to the humongous volumes of transactions. The proposed approach tends to capture much more fraud events in comparison with other conventional ML techniques. Our experimental evaluation exposes that our model exhibits a good performance in terms of recall and precision.

As integrated circuit technologies are moving to smaller technology nodes, Electromigration (EM) has become one of the most challenging problems facing the EDA industry. While numerical approaches have been widely deployed since they can handle complicated interconnect structures, they tend to be much slower than analytical approaches. In this paper, we present a fast semi-analytical approach, based on the matrix exponential, for the solution of Korhonen's stress equation at discrete spatial points of interconnect trees, which enables the analytical calculation of EM stress at any time and point independently. The proposed approach is combined with the extended Krylov subspace method to accurately simulate large EM models and accelerate the calculation of the final solution. Experimental evaluation on OpenROAD benchmarks demonstrates that our method achieves 0.5% average relative error over the COMSOL industrial tool while being up to three orders of magnitude faster.

Efficient sound density simulation for room acoustic models is a challenging problem, due to the need for the solution of large-scale systems of equations that require unreasonably long computational times. However, in many cases, the measurement of sound density is not required to be computed at every point of the entire room but only at certain spots. This makes the room acoustic problem amenable to Model Order Reduction (MOR) techniques. Moment-Matching (MM) techniques are well established and can be directly applied in the resulting sound diffusion equation. In this paper, we propose a computationally efficient MM algorithm based on extended Krylov subspace method, that can generate very compact models in order to efficiently simulate them across many time-steps. Experimental results demonstrate a speedup up to 1016× with relative error less than 0.5%.

With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ramps, while gate-interconnect interdependencies are stronger. Moreover, efficiency is a serious concern since repeatedly invoking a signoff tool during incremental optimization of modern VLSI circuits has become a major bottleneck. In this paper, we introduce a novel machine learning approach for timing estimation of gate-level stages using current source models and the concept of multiple slew and effective capacitance values. First, we exploit a fast iterative algorithm for initial stage timing estimation and feature extraction, and then we employ four artificial neural networks to correlate the initial delay and slew estimates for both the driver and interconnect with golden SPICE results. Contrary to prior works, our method uses fewer and more accurate features to represent the stage, leading to more efficient models. Experimental evaluation on driver-interconnect stages implemented in 7 nm FinFET technology indicates that our method leads to 0.99% (0.90 ps) and 2.54% (2.59 ps) mean error against SPICE for stage delay and slew, respectively. Furthermore, it has a small memory footprint (1.27 MB) and performs 35× faster than a commercial signoff tool. Thus, it may be integrated into timing-driven optimization steps to provide signoff accuracy and expedite timing closure.

As integrated circuit technologies move below 10 nm, Electromigration (EM) has become an issue of great concern for the longterm reliability due to the stricter performance, thermal and power requirements. The problem of EM becomes even more pronounced in power grids due to the large unidirectional currents flowing in these structures. The attention for EM analysis during the past years has been drawn to accurate physics-based models describing the interplay between the electron wind force and the back stress force, in a single Partial Differential Equation (PDE) involving wire stress. In this paper, we present a fast semi-analytical approach for the solution of the stress PDE at discrete spatial points in multi-segment lines of power grids, which allows the analytical calculation of EM stress independently at any time in these lines. Our method exploits the specific form of the discrete stress coefficient matrix whose eigenvalues and eigenvectors are known beforehand. Thus, a closed-form equation can be constructed with almost linear time complexity without the need of time discretization. This closed-form equation can be subsequently used at any given time in transient stress analysis. Our experimental results, using the industrial IBM power grid benchmarks, demonstrate that our method has excellent accuracy compared to the industrial tool COMSOL while being orders of magnitude times faster.

Traditional processor architectures utilize an external DRAM for data storage, while they also operate under worst-case timing constraints. Such designs are heavily constrained by the delay costs of the data transfer between the core pipeline and the DRAM, and they are incapable of exploiting the timing variations of their pipeline stages. In this work, we focus on a near-data processing methodology combined with a novel timing analysis technique that enables the adaptive frequency scaling of the core clock and boosts the performance of low-power designs. We propose a near-data processing and better-than-worst-case co-design methodology to efficiently move the instruction execution to the DRAM side and, at the same time, to allow the pipeline to operate at higher clock frequencies compared to the worst-case approach. To this end, we develop a timing analysis technique, which evaluates the timing requirements of individual instructions and we dynamically scale the clock frequency, according to the instructions types that currently occupy the pipeline. We evaluate the proposed methodology on six different RISC-V post-layout implementations using an HMC DRAM to enable the processing-in-memory (PIM) process. Results indicate an average speedup factor of 1.96× with a 1.6× reduction in energy consumption compared to a standard RISC-V PIM baseline implementation.

During the past decade, Model Order Reduction (MOR) has become key enabler for the efficient simulation of large circuit models. MOR techniques based on moment-matching are well established due to their simplicity and computational performance in the reduction process. However, moment-matching methods based on the ordinary Krylov subspace are usually inadequate to accurately approximate the original circuit behaviour. In this paper, we present a moment-matching method which is based on the extended Krylov subspace and exploits the superposition property in order to deal with many terminals. The proposed method can handle large-scale regular and singular circuits, and generate accurate and efficient reduced-order models for circuit simulation. Experimental results on industrial IBM power grid benchmarks demonstrate that our method achieves an error reduction up to 83.69% over a standard Krylov subspace technique.

Programming, most recently in the form of Computational Thinking (CT), is emerging as a new subject in primary schools worldwide. By data-based decision making, teachers, as learning designers, make decisions on instruction design based on a broad range of evidence, such as student assessment scores and classroom teaching observations. Given the current limitations on conclusive, field-proven teaching practices and an underlying “culture” to use as a basis, we turn to pertinent empirical studies that the growing scientific interest on introducing programming in primary school curricula has produced. The hypothesis is that we may overcome the lack of extensive experience in designing a programming course by reviewing the above evidence, in order to frame learning situations and methods.

The integration of more components into modern integrated circuits (ICs) has led to very large RLC parasitic networks consisting of millions of nodes that have to be simulated in many times or frequencies to verify the proper operation of the chip. Model order reduction (MOR) techniques have been employed routinely to substitute the large-scale parasitic model with a model of lower order with a similar response at the input-output ports. However, established MOR techniques generally result in dense system matrices that render their simulation impractical. To this end, in this article, we propose a methodology for the sparsification of the dense circuit matrices resulting from MOR of general RLC circuits, which employs a sequence of algorithms based on the computation of the nearest diagonally dominant matrix and the sparsification of the corresponding graph. In addition, we describe a procedure for synthesizing the sparsified reduced-order model into an RLC circuit with only positive elements. Experimental results indicate that a high sparsity ratio of the reduced system matrices can be achieved with very small loss of accuracy.

As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are more resistive, signals no longer resemble saturated ramps, and gate input pins exhibit a significant Miller effect. Over recent years, the semiconductor industry has adopted current source models (CSMs) for accurate gate modeling. Industrial gate models, however, are precharacterized assuming capacitive loads, which poses significant challenges to the approximation of the highly resistive load interconnect with an effective capacitance ( Ceff). In fact, most related works are either computationally expensive or unable to approximate the output slew. Furthermore, they require additional precharacterization and ignore the Miller effect. In this article, we present an iterative methodology for fast and accurate gate delay estimation. The proposed approach accurately computes the driver output waveform, using closed-form formulas to calculate a Ceffper waveform segment, while accounting for their interdependence. Thus, it allows for variable analysis resolution exploiting an accuracy/runtime tradeoff. In contrast to prior works, our approach is compatible with conventional CSMs and considers the impact of Miller capacitance. We evaluate our method on representative driver-load test circuits consisting of interconnects with arbitrary RC characteristics and ASU ASAP 7-nm standard cells. The proposed method achieves 1.3% and 2.5% delay and slew root-mean-square percentage error (RMSPE) against SPICE, respectively. In addition, it provides high efficiency, as it converges in 2.3 iterations on average.

Photovoltaic Solar Energy (PSE) sector has gained great attention during the last decades due to its significant role in the transition to sustainable energy systems. As a viable energy option, PSE has the potential to meet many of the challenges facing the world, along with the diminution of world’s dependency to fossil fuels, greenhouse gas emissions reduction and global warming mitigation. In the case of Brazil, the adoption of photovoltaic solar energy is mainly driven by the shortages and several other barriers that are met in the Brazilian energy sector. The development of the Brazilian PSE is the main concern of this study, and authors focus on the investigation of certain factors and their influence on this main outcome with the use of Fuzzy Cognitive Maps (FCMs). FCM is a well-established methodology for scenario analysis and management in diverse domains, and is based on fuzzy logic and neural networks aspects. In this paper we report particularly on the application of a new web-based software tool, called "FCMWizard", which can model complex and dynamic systems, implement several hypotheses and run various scenarios, helping decision-makers and stakeholders with the policy-making and energy management process. In this context, a semi-quantitative model was designed, which comprises 10 key concepts and three plausible scenarios were further conducted. The findings of this study highlight the economic and political influence on the development of the PSE sector in Brazil.

The Cloud infrastructure offers to end users a broad set of heterogenous computational resources using the pay-as-you -go model. These virtualized resources can be provisioned using different pricing models like the unreliable model where resources are provided at a fraction of the cost but with no guarantee for an uninterrupted processing. However, the enormous gamut of opportunities comes with a great caveat as resource management and scheduling decisions are increasingly complicated. Moreover, the presented uncertainty in optimally selecting resources has also a negatively impact on the quality of solutions delivered by scheduling algorithms. In this paper, we present a dynamic scheduling algorithm (i.e., the Uncertainty-Driven Scheduling - UDS algorithm) for the management of scientific workflows in Cloud. Our model minimizes both the makespan and the monetary cost by dynamically selecting reliable or unreliable virtualized resources. For covering the uncertainty in decision making, we adopt a Fuzzy Logic Controller (FLC) to derive the pricing model of the resources that will host every task. We evaluate the performance of the proposed algorithm using real workflow applications being tested under the assumption of different probabilities regarding the revocation of unreliable resources. Numerical results depict the performance of the proposed approach and a comparative assessment reveals the position of the paper in the relevant literature.

During the past decade, model order reduction (MOR) has become key enabler for the efficient simulation of large circuit models. MOR techniques based on balanced truncation (BT) offer very good error estimates and can provide compact models with any desired accuracy over the whole range of frequencies (from dc to infinity). However, in most applications the circuit is only intended to operate at specific frequency windows, which means that the reduced-order model can become unnecessarily large to achieve approximation over all frequencies. In this article, we present a frequency-limited approach which, combined with an efficient low-rank sparse implementation of the extended Krylov subspace (EKS) method, can handle large input models and provably leads to reduced-order models that are either smaller or exhibit better accuracy than full-frequency BT.

The integration of more components into ICs due to the ever increasing technology scaling has led to very large parasitic networks consisting of million of nodes, which have to be simulated in many times or frequencies to verify the proper operation of the chip. Model Order Reduction techniques have been employed routinely to substitute the large scale parasitic model by a model of lower order with similar response at the input/output ports. However, all established MOR techniques result in dense system matrices that render their simulation impractical. To this end, in this paper we propose a methodology for the sparsification of the dense circuit matrices resulting from Model Order Reduction, which employs a sequence of algorithms based on the computation of the nearest diagonally dominant matrix and the sparsification of the corresponding graph. Experimental results indicate that a high sparsity ratio of the reduced system matrices can be achieved with very small loss of accuracy.

The integration of more components into modern Systems-on-Chip (SoCs) has led to very large RLC parasitic networks consisting of million of nodes, which have to be simulated in many times or frequencies to verify the proper operation of the chip. Model Order Reduction techniques have been employed routinely to substitute the large scale parasitic model by a model of lower order with similar response at the input/output ports. However, all established MOR techniques result in dense system matrices that render their simulation impractical. To this end, in this paper we propose a methodology for the sparsification of the dense circuit matrices resulting from Model Order Reduction of general RLC circuits, which employs a sequence of algorithms based on the computation of the nearest diagonally dominant matrix and the sparsification of the corresponding graph. Experimental results indicate that a high sparsity ratio of the reduced system matrices can be achieved with very small loss of accuracy.

The verification of integrated Circuits (ICs) in deep submicron technologies requires that all mutual inductive effects are taken into account to properly validate the performance and reliable operation of the chip. However, the inclusion of all mutual inductive couplings results in a fully dense inductance matrix that renders the circuit simulation computationally prohibitive. In this paper, we present efficient techniques for the solution of the linear systems arising in transient analysis of large mutually inductive circuits. These techniques involve the compression of the dense inductance matrix block by low-rank products in hierarchical matrix format, as well as the development of a Schur-complement preconditioner for the iterative solution of the transient linear system (which comprises sparse blocks alongside the dense inductance block). Experimental results indicate that substantial compression rates of the inductance matrix can be achieved without compromising accuracy, along with considerable reduction in iteration counts and execution time of iterative solution methods.

Data stream processing has received considerable attention from both research community and industry over the last years. Since latency is a key issue in data stream processing environments, the majority of the works existing in the literature focus on minimizing the latency experienced by the users. The aforementioned minimization takes place by assigning the data stream processing components close to data sources. Server consolidation is also a key issue for drastically reducing energy consumption in computing systems. Unfortunately, energy consumption and latency are two objective functions that may be in conflict with each other. Therefore, when the target function is to minimize energy consumption, the delay experienced by users may be considerable high, and the opposite. For the above reason there is a dire need to design strategies such that by targeting the minimization of energy consumption, there is a graceful degradation in latency, as well as the opposite. To achieve the above, we propose a Pareto-efficient algorithm that tackles the problem of data processing tasks placement simultaneously in both dimensions regarding the energy consumption and latency. The proposed algorithm outputs a set of solutions that are not dominated by any solution within the set regarding energy consumption and latency. The experimental results show that the proposed approach is superior against single-solution approaches because by targeting one objective function the other one can be gracefully degraded by choosing the appropriate solution.

Manufacturing process variation in sub-20nm processes has introduced ever increasing overhead in Static Timing Analysis (STA) in order to guarantee the reliable operation of the circuit. Chip designers apply corner-based analysis and add guard-bands to design parameters in order to take into account the impact of process variation on timing. However, the aforementioned techniques are either too slow as the number of design parameters proliferates with the integration of more components into a chip or inaccurate due to the assumption that the worst case delay resides at the corners of design parameters. In this paper, we present a novel statistical methodology, which relies on Extreme Value Theory (EVT), to estimate the worst case delay of VLSI circuits under variations in gate/interconnect parameters. Despite the previous statistical approaches toward maximum delay estimation, our methodology can be applied regardless of the underlying gate/interconnect delay model or any assumption about the distribution of the Arrival Time (AT) at every circuit node, making it very appealing for integration to any level of timing analysis abstraction (from spice-to-gate level) and provide fast yet accurate results. Experimental results on ISCAS85/ISCAS89 circuits show that the estimated maximum AT at the Primary Outputs (POs) can be within 5% of the true maximum AT, at the cost of a few thousand Monte Carlo simulations.

Popular interest in robotics has increased significantly over the last years. It has been claimed that robotics can provide new benefits to the learning process at all levels of education. The main ideas of the present study adhered to the constructionist theory, according to which the learning process is not only transmitted from teacher to pupil, but rather constructed in the mind of the pupil in the form of active learning. The purpose of the present study was to implement a robotic toy (Lego Mindstorms NXTTM) in a Greek primary school, in order to teach twelve year-old children some of the basic concepts of geometry. The main hypothesis of the present study was that children who used the Lego Mindstorms NXT platform would score higher on an evaluation questionnaire than children who formed the control group. Descriptive statistical analysis was performed in order to evaluate the correct answers of the questionnaires. Statistical analysis revealed that children who participated in the experimental group performed better in the 21 items of the questionnaire. Moreover, they mentioned that the geometry course became more interesting and drew their attention in comparison to the courses that were taught through the standard teaching process. It is apparent that the present study follows the line of inquiries that supports that robotics can make a significant impact to education. Robots can be a tool that can enhance the skills of children.

Dyscalculia is a neurodevelopmental disorder that affects the ability of a child to learn arithmetic. Dyscalculia appears despite normal intelligence, proper schooling, adequate environment, socioeconomic status and motivation. The first aim of the present research protocol was to construct a battery of tests that can be delivered by computer in order to screen children's arithmetic skills. Our second aim was to develop a web application screener for dyscalculia that assesses children aged from 8–11 years old and that, to the best of our knowledge, does not exist. The hypothesis of the present study was that Greek students that are already diagnosed by paper-and-pencil tests as dyscalculic, will present lower performance and higher time latencies in the tasks of the aforementioned web application screener. A total of sixty, right handed children (30 male and 30 female, age range 8–11 years old) participated in this study. The students with disorders in mathematics (N=30, 15 male and 15 female) had a statement of dyscalculia issued after assessment at a Centre of Diagnosis, Assessment and Support, as required by Greek Law. The comparison group (N=30) was formed by pupils who attended the same classes with dyscalculics, presented typical academic performance according to their teachers' ratings and had been matched for age and gender with the children with disorder in mathematics. Three tasks were used for evaluating children's arithmetic ability: a calculation task, a task that evaluated their skills in understanding mathematical terminology, and an arithmetic problem solving task. Statistical analysis revealed that children with dyscalculia had statistically significant lower mean scores of correct answers and larger time latencies in all tasks compared to their average peers that participated in the comparison group. In conclusion, it must be highlighted that the web application screener for dyscalculia used in this study was found to be a feasible instrument for first-pass screening services and referral.

Several virtual machine (VM) placement algorithms have been proposed and studied in the literature with various scopes such as server consolidation or network cost minimization. In most cases, decisions on VM migrations are taken without factoring in directly the data access cost by VMs. In this paper, we investigate the use of data replication in conjunction with the VM assignment problem and target on developing algorithms that decide both on which data should be replicated where and which VM must be migrated so as to minimize the network overhead among traditional cloud and mobile cloud systems. We discuss both the un-capacitated case and the more realistic case whereby datacenters (for the traditional cloud case) and micro-datacenters (for the mobile cloud case) have limited storage and computing capacity. We propose an algorithm based on hyper-graph partitioning to solve the aforementioned problem in an optimal way regarding the unconstrained case and extend it to capture storage and computing capacity constraints. Experimental evaluation shows that the proposed algorithm yields up to 53 percent network overhead reduction when compared to state-of-the-art algorithms found in the literature.

Efficient analysis of on-chip power delivery networks is one of the most challenging problems facing the electronic design automation industry today. The fast dc and transient simulation of power grids is necessary to determine the proper operation of the integrated circuits at the design phase, but is made very difficult by the sheer size of modern power grids, reaching quite a few million nodes in nanometer-scale integrated circuits. This paper presents two efficient and highly parallel preconditioning mechanisms for the analysis of large-scale power grids of near-2-D structure (with small via resistances) or 3-D structure (with large via resistances) by iterative solution methods. The proposed preconditioners approximate the matrices of practical power grids well enough to ensure fast convergence of the iterative method, while their application within the core of the method is based on a fast transform solver which makes use of a series of independent fast Fourier transforms. Apart from the near-optimal operation complexity, the main characteristics of a fast transform solver are the large degree of multilevel parallelism and low memory requirements, which enable harnessing the computational resources of massively parallel architectures like graphics processing units (GPUs). Experimental evaluation of the proposed methodology on a set of large-scale industrial benchmarks demonstrates nearly two orders of magnitude speedup and reduction in memory footprint over parallel implementations of state-of-the-art direct and iterative methods, when GPUs are utilized.

The inverse of the inductance matrix (reluctance matrix) is amenable to sparsification to a much greater extent than the inductance matrix itself. However, the inversion and subsequent truncation of a large dense inductance matrix to obtain the sparse inverse is very time-consuming, and previously proposed window-based techniques cannot provide adequate accuracy. In this paper we propose a method for selective inversion of the inductance matrix to a prescribed sparsity ratio, which is also amenable to parallelization on modern architectures. Experimental results demonstrate its potential to provide efficient and accurate approximation of the reluctance matrix for simulation of large-scale RLC circuits.

As integrated circuit process technology progresses into the deep sub-micron region, the phenomenon of process variation has a growing impact on the design and analysis of digital circuits and more specifically in the accuracy and integrity of timing analysis methods. The assumptions made by the analytical models, impose excessive and unwanted pessimism in timing analysis. Thus, the necessity of removing the inherited pessimism is of utmost importance in favour of accuracy. In this paper an approach to the common path pessimism removal timing analysis problem, TKtimer, is presented. By utilizing certain key techniques such as branch-and-bound, caching, tasklevel parallelism and enhanced algorithmic techniques, the approach described by this paper is able to handle any type and size of clock network trees and showed 100% accuracy combined with reasonable execution time within a straightforward solution context.

This paper introduces a novel approach towards the statistical analysis of modern high-speed I/O and similar communication links, which is capable of reliably to determine extremely low (∼10−12or lower) bit error rates (BER) by using techniques from extreme value theory (EVT). The new method requires only a small amount of voltage values at the received eye center, which can be generated by running circuit/system level simulations or measuring fabricated I/O circuits, to predict link BERs. Unlike conventional techniques, no simplifying assumptions on link noise and interference sources are required making this approach extremely portable to any communication system operating with very low BER. Our experimental results show that the BER estimates from the proposed methodology are on the same order of magnitude as traditional time domain, transient eye diagram simulations for links with BER of 10−6and 10−5operating at 9.6 and 10.1 Gbps respectively.

Efficient analysis of massive on-chip power delivery networks is among the most challenging problems facing the EDA industry today. Due to Joule heating effect and the temperature dependence of resistivity, temperature is one of the most important factors that affect IR drop and must be taken into account in power grid analysis. However, the sheer size of modern power delivery networks (comprising several thousands or millions of nodes) usually forces designers to neglect thermal effects during IR drop analysis in order to simplify and accelerate simulation. As a result, the absence of accurate estimates of Joule heating effect on IR drop analysis introduces significant uncertainty in the evaluation of circuit functionality. This work presents a new approach for fast electrical-thermal co-simulation of large-scale power grids found in contemporary nanometer-scale ICs. A state-of-the-art iterative method is combined with an efficient and extremely parallel preconditioning mechanism, which enables harnessing the computational resources of massively parallel architectures, such as graphics processing units (GPUs). Experimental results demonstrate that the proposed method achieves a speedup of 66.1X for a 3.1M-node design over a state-of-the-art direct method and a speedup of 22.2X for a 20.9M-node design over a state-of-the-art iterative method when GPUs are utilized.

Efficient analysis of massive on-chip power delivery networks is among the most challenging problems facing the EDA industry today. In this paper, we present a new preconditioned iterative method for fast DC and transient simulation of large-scale power grids found in contemporary nanometer-scale ICs. The emphasis is placed on the preconditioner which reduces the number of iterations by a factor of 5X for a 2.6M-node industrial design and by 72.6X for a 6.2M-node synthetic benchmark, compared with incomplete factorization preconditioners. Moreover, owing to the preconditioner's special structure that allows utilizing a Fast Transform solver, the preconditioning system can be solved in a near-optimal number of operations, while it is extremely amenable to parallel computation on massively parallel architectures like graphics processing units (GPUs). Experimental results demonstrate that our method achieves a speed-up of 214.3X and 138.7X for a 2.6M-node industrial design, and a speed-up of 1610.5X and 438X for a 3.1M-node synthetic design, over state-of-the-art direct and iterative solvers respectively when GPUs are utilized. At the same time, its matrix-less formulation allows for reducing the memory footprint by up to 33% compared to the memory requirements of the best available iterative solver.

Validating the robustness of power distribution in modern IC design is a crucial but very difficult problem, due to the vast number of possible working modes and the high operating frequencies which necessitate the modeling of power grid as a general RLC network. In this paper we provide a characterization of the worst-case current waveform excitations that produce the maximum voltage drop among all possible working modes of the IC. In addition, we give a practical methodology to estimate these worst-case excitations on the basis of a sample of the excitation space acquired via plain circuit simulation. In the course of characterizing the worst-case excitations we also establish that the voltage drop function for RLC grid models has nonnegative coefficients, which has been an open problem so far.

In this work, we present a hardware architecture prototype for the various types of transforms and the accompanying quantization, supported in H.264 baseline profile video encoding standard. The proposed architecture achieves high performance and can satisfy quad full high definition (QFHD) (3840middot2160@150Hz) coding. The transforms are implemented using only add and shift operations, which reduces the computation overhead. A modification in the quantization equations representation is suggested to remove the absolute value and resign operation stages overhead. Additionally, a post-scale Hadamard transform computation is presented. The architecture can achieve a reduction of about 20% in power consumption, compared to existing implementations.

Accurate simulation of digital circuits is an essential part of the design process. High precision models are generally used to confirm logic behavior and estimate power dissipation, which has become an extremely important design parameter. Unfortunately high precision analysis is expensive in computer execution time, and there is always a trade-off between accuracy and speed. This work proposes a new circuit simulation approach by storing a set of pre-characterized transition configurations for each standard library cell in a lookup table. The lookup table contains information about the voltage and the current transient waveform produced by SPICE simulation. The method achieves good accuracy levels for yielding the total or partial current waveform of a circuit in significantly less time compared to SPICE or other commercial tools.

The H.264 video coding standard can achieve considerably higher coding efficiency than previous video coding standards. The keys to this high coding efficiency are the two prediction modes (Intra & Inter) provided by H.264 which adopt many new features such as variable block size searching, motion vector prediction etc. However, these result in a considerably higher encoder complexity that adversely affects speed and power, which are both significant for the mobile multimedia applications targeted by the standard. Therefore, it is of high importance to design architectures that minimize the speed and power overhead of the prediction modes. In this paper we present a new algorithm, and the architecture that implements it, that can replace the standard sum of absolute differences (SAD) approach in the two main prediction modes, supports the variable block size motion estimation (VBSME) as it is defined in the standard and provide a power efficient hardware implementation without perceivable degradation in coding efficiency or video quality.

Identifying worst-case voltage drop conditions in every module supplied by the power grid is a crucial problem in modern IC design. In this paper we develop a novel methodology for power grid verification which is based on accurately constructing the space of current variations of the supplied modules and locating its precise points that yield the worst-case voltage drop conditions. The construction of the current space is performed via plain simulation and statistical extrapolation using results from extreme value theory. The method overcomes limitations of past methods which either relied on loosely bounding the worst-case voltage drop, or abstracted the current space in a vague and incomplete set of bound-type constraints. Experimental results verify the potential of the proposed method to identify worst-case conditions and demonstrate the pessimism inherent in previous bound-type approaches.

The H.264 video coding standard can achieve considerably higher coding efficiency than previous video coding standards. The keys to this high coding efficiency are the two prediction modes (Intra & Inter) provided by H.264. Unfortunately, these result in a considerably higher encoder complexity that adversely affects speed and power, which are both significant for the mobile multimedia applications targeted by the standard. Therefore, it is of high importance to design architectures that minimize the speed and power overhead of the prediction modes. In this paper we present a new algorithm, and the logic transformations that enable it, that can replace the standard Sum of Absolute Differences (SAD) approach in the two main prediction modes, and provide a power efficient hardware implementation without perceivable degradation in coding efficiency or video quality.

The problem of optimum design of tree-shaped power distribution networks with respect to the voltage drop effect is addressed in this paper. An approach for the width adjustment of the power lines supplying the circuit's major functional blocks is formulated, so that the network occupies the minimum possible area under specific voltage drop constraints at all blocks. The optimization approach is based on precise maximum current estimates derived by statistical means from recent advances in the field of extreme value theory. Experimental tests include the design of power grid for a choice of different topologies and voltage drop tolerances in a typical benchmark circuit.

A Monte Carlo approach for maximum power estimation in CMOS very large scale integration (VLSI) circuits is proposed. The approach is based on the largely unexploited area of statistics known as extreme value theory. Within this framework, it attempts to appropriately model the extreme behavior of the probability distribution of the peak instantaneous power drawn from the power supply bus, in order to yield a close estimate of its maximum possible value. The approach features a relatively small number of necessary input patterns that does not depend on the circuit size, user-specified accuracy, and confidence levels for the final estimate, simplicity in the algorithmic implementation, noniterative single-loop execution, highly accurate simulation-based operation, and easy integration within the design flow of CMOS VLSI circuits. Experimental results establish the above claims and demonstrate the overall efficiency of the proposed approach to address the problem of maximum power estimation.

In this paper, we focus on low-power design techniques for high-performance processors at the architectural and compiler levels. We focus mainly on developing methods for reducing the energy dissipated in the on-chip caches. Energy dissipated in caches represents a substantial portion in the energy budget of today's processors. Extrapolating current trends, this portion is likely to increase in the near future, since the devices devoted to the caches occupy an increasingly larger percentage of the total area of the chip. We propose a method that uses an additional minicache located between the I-Cache and the central processing unit (CPU) core and buffers instructions that are nested within loops and are continuously otherwise fetched from the I-Cache. This mechanism is combined with code modifications, through the compiler, that greatly simplify the required hardware, eliminate unnecessary instruction fetching, and consequently reduce signal switching activity and the dissipated energy. We show that the additional cache, dubbed L-Cache, is much smaller and simpler than the I-Cache when the compiler assumes the role of allocating instructions to it. Through simulation, we show that for the SPECfp95 benchmarks, the I-Cache remains disabled most of the time, and the "cheaper" extra cache is used instead. We also propose different techniques that are better adapted to nonnumeric nonloop-intensive code.

Article Quasi-static energy recovery logic and supply-clock generation circuits Share on Authors: Yibin Ye School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN School of Electrical and Computer Engineering, Purdue University, West Lafayette, INView Profile , Kaushik Roy School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN School of Electrical and Computer Engineering, Purdue University, West Lafayette, INView Profile , Georgios I. Stamoulis Low Power Design Technology, Intel Corp., Santa Clara, CA Low Power Design Technology, Intel Corp., Santa Clara, CAView Profile Authors Info & Claims ISLPED '97: Proceedings of the 1997 international symposium on Low power electronics and designAugust 1997 Pages 96–99https://doi.org/10.1145/263272.263293Online:01 August 1997Publication History 7citation262DownloadsMetricsTotal Citations7Total Downloads262Last 12 Months2Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

In this paper, a new approach is presented for estimating the hot-carrier induced degradation in MOS transistors in VLSI circuits. With the decrease in feature size, many long-term reliability issues, such as HCE (Hot-Carrier Effect), TDDB (Time-Dependent Dielectric Breakdown), etc., can no longer be ignored during the design process. In this work we mainly concentrate on HCE; however, the approach can be applied to investigate other reliability issues. HCE is a long-term reliability issue that is caused by the cumulative effects of all possible inputs on the devices in the circuit over time. Existing techniques use deterministic circuit or timing simulation to estimate HCE and try to predict the age of the design by incorporating device degradation over time. As a result, all HCE simulators are too slow (especially if linked to SPICE-circuit simulators) for large circuits; and even when fast simulation techniques are used, user-specified deterministic input waveforms are needed and, hence, the results can only represent a small sample of operating conditions. In this paper, we propose a probabilistic timing approach. The advantage of probabilistic simulation is that we can explore the cumulative effects of all possible input waveform combinations in one run. The approach has been implemented in a general-purpose simulator and tested on a number of typical examples and benchmarks.>

Probabilistic simulation has been shown to be a very cost-effective approach to the computation of voltage and current waveform statistics in CMOS digital circuits, compared to exhaustive simulation.Thk approach is particularly attractive when long-term reliability issues such as electromigration, hot-carrier effects, and average power, are to be estimated over all possible input signals.In this paper we present new algorithms for performing probabilistic simulation that provide significant improvements over existing ones, both in accuracy and speed.The improvements are carried out at the subcircuit level,where the statistics of the current and voltage waveforms and the delays are computed more accurately, and at the global level, where signal correlations are considered.The new algorithms have been implementedin a computer program and tested on a number of large benchmark circuits.I.

An approach for estimating hot-carrier induced degradation in MOS transistor circuits is presented. The approach uses probabilistic timing simulation techniques to estimate the cumulative effects of all possible inputs on hot-carrier effect (HCE) degradation in each transistor in the circuit in a single run rather than using exhaustive or Monte Carlo simulations. The approach has been implemented in a general-purpose simulator and tested on a number of typical examples and benchmarks.>