The article presents the design and the architectural optimization of a new Hybrid, High-Resolution Digital Pulse Width Modulator (HHR-DPWM) and its implementation in an integrated, digitally-controlled, voltage-mode, point-of-load (POL) buck converter for automotive applications. The pro-posed HHR-DPWM architecture, which features a synchronous counter-based DPWM, a delay locked loop (DLL)-based digital-to-time converter (DTC) with sub-clock-cycle resolution, and Dyadic Digital Pulse Modulation (DDPM) dithering, is optimized to meet the requirements of the POL converter at low cost and design effort. The POL converter with the proposed HHR-DPWM is fabricated in the 110 nm BCD9s technology by STMi-croelectronics. Based on measurements, the converter regulates the output voltage with 2 mV accuracy, 2 mV peak to peak ripple and a power efficiency up to 95.4% at 3.4 V output voltage.

A wide range of tools, machines from diverse industries are operated by the precise rotation of physical devices (e.g., knobs, encoders). Literature proved that Mixed Reality can provide rotation guidance by superimposing digital cues onto the real environment. However, existing studies primarily focus on speed rather than precision and lack proven solutions with standard comparison methods. We presented a novel open MR testbed to evaluate MR rotation guidance cue designs. It comprises (i) a 3D-printed structure with a controller mount for MR cue tracking, (ii) an industrial encoder (resolution 1.8º), (iii) an Esp32 microcontroller, (iv) a firmware for USB connection, and (v) a USB foot pedal to confirm rotation, (vi) test software and documentation. The testbed uses available off-the-shelf components, and it is distributed with an open source license, Unity package with cues examples and scripts for running tests with randomized targets and collecting performance data (error count and speed). We evaluated the MR testbed by comparing the Arrow cue (baseline) and two novel designs: Magnifier with a zoomed region and Gestalt leveraging related perception principles. A within-subjects study ($\mathrm{N}=36,180^{\prime \prime}, 18$ọ,$\mathrm{M}=27.58, \pm 3.55$) showed that the Magnifier is the most precise ($p<.001$), while the Gestalt is the fastest ($p<.001$). Moreover, males (higher motor and gaming skills) ($\mathrm{p}<.002, \mathrm{t}=3.89$) resulted in faster ($\mathrm{r}=-0.458, \mathrm{p}<$. 005). Participants who declared with higher gaming skills demonstrated less task load during the experiment ($\mathrm{r}=+0.548, \mathrm{p}<.005$). Overall, the participants slightly preferred the Gestalt (18) over the Magnifier (15), while the Arrow was selected by a few (3). Ultimately, the testbed has proven to be an effective research and evaluation platform for future mixed reality interfaces.

A Relaxation Digital-to-Analog Converter (ReDACs) with a novel, all-digital, radix-based digital correction technique for clock-indifferent linear operation is presented in this paper. The ReDAC architecture proposed in this paper does not require dedicated circuit for frequency tuning, and achieves linearity by digitally pre-processing the DAC input code by a Radix-based Digital Correction (RBDC) algorithm. The effectiveness of the proposed RBDC approach is demonstrated by transistor level simulations on a 10-bit, 1.7MS/s ReDAC in 180nm CMOS. Thanks to the proposed RBDC, under a 16% deviation from the ideal clock period, the maximum INL of the ReDAC is improved from 79.4 to 1.01LSB, its maximum DNL is improved from 158.3 to 0.45LSB and its SNDR is increased from 22.2 (3.4 ENOB) to 58.5dB (9.4 ENOB), at the cost of an increased power consumption from $1.85 \mu \mathrm{W}$ to $9.15 \mu \mathrm{W}$.

In this paper, the implementation on a Field Programmable Gate Array (FPGA) of Relaxation Digital to Analog Converters (ReDACs), which take advantage of the impulse response of a first-order RC network to generate and combine binary weighted voltages, is addressed. For this purpose, the dominant ReDAC nonlinearity limitation related to the parasitics of the RC network is analyzed and a simple and robust technique for its effective suppression is proposed. Moreover, a ReDAC foreground digital calibration strategy suitable to FPGA implementation is introduced to tune the clock frequency of the converter, as requested for ReDAC operation. The novel error suppression technique and calibration strategy are finally implemented on a 13-bit, 514 S/s prototype (ReDAC1) and on a 11-bit, 10.5 kS/s prototype (ReDAC2), which are experimentally characterized under static and dynamic conditions. Measured results on ReDAC1 (ReDAC2) reveal 1.68 LSB (1.53 LSB) maximum INL, 1.54 LSB (1.0 LSB) maximum DNL, 76.4 dB (67.9 dB) THD, 79.7 dB (71.4 dB) SFDR and 71.3 dB (63.3 dB) SNDR, corresponding to 11.6 (10.2) effective bits (ENOB).

A reference-free, fully digital foreground self-calibration strategy intended to automatically tune the clock frequency of Relaxation Digital to Analog Converters (ReDACs), as demanded for linear operation, is presented in this paper. The effectiveness of the proposed approach is demonstrated by computer simulations on a 10-bit, 2MS/s ReDAC designed in 40nm CMOS and operated from a 600mV power supply voltage. After the proposed calibration, the ReDAC is shown to operate near the optimal clock frequency achieving 0.98 LSB maximum INL, 1.00 LSB maximum DNL and 9.06 ENOB.

The interference between switching mode power converters and wireline digital communications is addressed in this paper and the impact on communication errors of different Spread Spectrum (SS) modulation techniques, which are commonly used in power convertors to comply with EMC regulations, is experimentally investigated in a particular case. Experimental results do not highlight significant differences in terms of communication error rate induced in the victim data line between power converters featuring conventional and SS pulse width modulations.

This work presents a new methodology to derive the equivalent circuit of the parasitic paths that propagate switching noise in mixed-signals integrated circuits and that usually lead to unintended crosstalk and electromagnetic emission issues. The methodology is based on small-signal analyses performed at the individual analog and digital microcontroller building block level, on electromagnetic simulations carried out to describe the power supply network at the chip- and at the package-level and on the analysis of the chip layout and process technology data to model the parasitic coupling paths through the semiconductor substrate. The electrical model of microcontrollers generated according to this methodology, consists of a low-complex and linear netlist that provides insight regarding the relationships between the design parameters and noise propagation paths in the early design phases, through simulations in a SPICE-like environment. The proposed approach does not rely on experimental test results. In this paper, the electric model of an 8 bit microcontroller, which validity has been proved by scattering parameter and conducted emission measurements, is derived.

This paper deals with the characterization of integrated circuit electromagnetic emissions. The TEM cell method is employed in order to identify primary emission sources of complex digital devices. An 8-bit microcontroller, realized by a 0.8 /spl mu/m HCMOS process is considered. It is composed of several building blocks like the central processing unit, the analog to digital converter and the EPROM memory. Emission measurements are performed by operating a specific program code stored in the microcontroller memory and emissions due to each building block are identified.