We have proposed a digital frequency measurement technique with enhanced accuracy, exploiting FPGA Mixed-Mode Clock Management for QCM-D technology. In detail, the method is based on the multi-phase generalization of the basic direct period measurement technique, involving low-complexity digital architectures based on gated counters. Theoretical analysis has been validated by experimental results, referring to a design implemented on a Xilinx Artix-7 FPGA. The proposed solution allowed to reach a worst-case frequency measurement error of ≈ 20Hz for an observation period of$200\mu \mathrm{s}$of a damped QCM sensor resonating at 10MHz.

We discuss a novel investigation approach to study current limiting techniques for accurate memristor programming. In detail, referring to the case of the Stanford memristor model, we propose to analyze its programming dynamics adopting a nonlinear static analysis point of view and considering, for the sake of simplicity, the special case of a linear resistive current limiter.

We discuss a monitoring system aiming to select, among a set of integrated entropy sources affected by process variability, the source guarantying the highest worst-case entropy. The approach is particularly suitable when considering True Random Number Generators based on Digital Nonlinear Oscillators, since multiple instances of the entropy sources can be implemented at a reduced hardware cost. In general, the approach can be applied for TRNGs based on parametric systems, thus offering entropy tuning capabilities. The original theoretical results have been validated with experiments.

We discuss a stochastic algorithm to design tuning controllers for cryptographic True Random Number Generators, compliant to NIST recommendations, as an effective low-complexity solution to counteract entropy variability in integrated architectures implementing tunable entropy sources. Taking as a reference the min-entropy concept, we discussed the proposal from both the theoretical and hardware design points of view, validating claims with proofs and experiments. Depending on the target accuracy, the proposed architecture is scalable, and its profitable use in TRNG design strongly depends on the kind of core entropy sources taken into account. Furthermore, we show that the low-complexity entropy measurement techniques exploited in this proposal can be used to design a legitimate alternative to the Adaptive Proportion Health Test recommended in the NIST 800.90B publication.

We propose a novel class of Digital Nonlinear Oscillators (DNOs) supporting complex dynamics, including chaos, suitable for the definition of high-performance and low-complexity entropy sources in digital programmable devices. We derive our solution from the analysis of simplified models, proposing a low-complexity `fully digital' chaotic entropy source consuming few look-up tables in a Xilinx FPGA. The validity of the proposal has been verified with experiments.

We investigate and compare three low complexity circuit topologies to be implemented in programmable logic devices, for the design of True Random Bit Generators for Lightweight Cryptography. The architectures, based on the general idea of Digital Nonlinear Oscillators (DNOs), have been compared on the basis of measurement campaigns, carried out referring to figures of merit specifically introduced to assess the quality and reliability of the oscillators under test.

This paper considers the current mode CMOS circuit implementation of the Sawtooth Piecewise Linear chaotic map. Starting from circuit analysis, we discuss a theoretical model to investigate the effects on the dynamical system entropy caused by the map shape nonlinear distortion, introduced by the circuit implementation. The results offer the designer an investigation tool to properly manage some relevant trade-offs related to the CMOS circuit design, highlighting the most critical model parameters affecting the deterioration of the achievable system entropy.

Adopting a nonlinear dynamical system analysis point of view, we discuss the design of a low-complexity CMOS electronic circuit implementing a Physically Unclonable Function core module based on a two-neurons Cellular Neural Network. The study follows a theoretical approach investigating the circuit topology, aiming at proposing a methodological engineering approach for the design of this class of systems.

In this brief we outline a novel perspective for the design of True Random Number Generators in Programmable Logic Devices (PLDs), proposing to bring together PLD design, circuit modeling and the analysis of nonlinear dynamical systems. Although the discussion and experimental results provided in this work refer to FPGA design, the reasoning and concepts have general validity, being easily adaptable to other kind of PLDs, e.g., Complex PLDs (CPLDs). We introduce a novel class of systems, that have been generically named Digital Nonlinear Oscillators, exhibiting complex periodic dynamical behavior, proposing topologies based on Ring Oscillators embedded in looped structures using digital delay blocks and XOR gates. We compared the proposed systems with other solutions proposed in literature, discussing the circuit operation and its nonlinear dynamical behavior.

We discuss a novel measurement system based on passive Variable Reluctance Magnetic Sensors (VRSs) to provide clearance measurement for turbo-machine monitoring. The advantage of the solution is in its reliability and low-complexity (in terms of sensor structure, costs and electronic front-end), against an acceptable measurement accuracy, making the proposed method suitable for the condition monitoring of huge turbo-machines requiring a large number of sensors.

We propose to exploit a two-neurons Cellular Neural Network (CNN) to design a basic 1-bit Physically Unclonable Function (PUF). The analysis discussed in this work, derived from the general theory of CNNs, has been validated by experimental results.

We propose a compression method for True Random Bit Generators (TRBGs) that exploits pseudo-chaotic systems. The compression scheme requires extremely low-complex hardware circuits for being implemented whereas its theoretical explanation is based on a weaker and more general interpretation of the Shadowing Theory, focusing on probability measures, rather than on single chaotic trajectories. We prove theoretically how to design the overall compression scheme, in order to assure the final entropy of the compressed TRBG to be arbitrarily close to the maximum theoretical limit of 1 bit/time-step.

In this paper an efficient and accurate method for computing the invariant measure of piecewise affine chaotic maps is proposed. As an application example, the method is used to evaluate for a chaos-based true random bit generator the robustness of the entropy with respect to small map parameters variations.

In this paper a novel family of maximum-period nonlinear congruential generators (NLCGs) based on the digitized sawtooth map is considered for the definition of hardware and software efficient pseudo random number generators (PRNGs). A list of such maximum period NLCGs for period lengths up to 231-1 is provided. Referring to the NIST800-22 statistical test suite, a PRNG example based on the combination of two of the proposed NLCGs is presented and discussed

In this paper the theoretical bases to design a true random bit generator (TRBG) circuit with a predefined minimum entropy are discussed. The approach is tailored to TRBGs based on a one-dimensional piecewise-linear chaotic map, and it is based on a feedback control procedure that allows to dynamically changing the system parameters. For this purpose, the procedure just exploits the TRBG output observation without requiring bit throughput reduction. The design approach was validated by an hardware prototype implemented on a field programmable analog array (FPAA)