A low-power motion estimation chip is designed for a wireless panoramic endoscope system. This chip consists of two motion estimation cores and is implemented by a dual-Vdd low-power technique. The proposed technique is efficient in decreasing power consumption without reducing the operation frequency of the chip. From the full-function chip measurements, this dual-Vdd chip can reduce power consumption by 20%~40% than the operation in single-Vdd for different clock frequencies.

A low-power motion estimation chip is designed for a wireless panoramic endoscope system. This chip consists of two motion estimation cores and is implemented by a dual-Vdd low-power technique. The proposed technique is efficient in decreasing power consumption without reducing the operation frequency of the chip. From the full-function chip measurements, this dual-Vdd chip can reduce power consumption by 20%∼40% than the operation in single-Vdd at different clock frequencies.

Light Detection and Ranging (LiDAR) is a high-price system for wide-usage automotive driving requirements. The design, implementation, and validation of a performance-complexity efficient LiDAR system are introduced in this paper. A Time-to-Digit (TDC) chip with a low-cost Data-Processing (DP) chip is utilized in this system. The proposed chips have been well validated and can be utilized as processing cores for a generic LiDAR system. The measurement accuracy is a comparison with a high-price commercial product of Time-Correlated Single-Photon-Counting (TCSPC). The values show the proposed system accuracy is respectable for the comparison by many distances from 4.8m to 44.6m, the maximum difference is 0.3%.

It is generally accepted that robotic surgery has increased in popularity which has revolutionized the medical field over the past few decades. Despite many successes and development, there are still a lot of challenges what was remained in the surgeries such as the requirement of haptic feedback system has become a raising issue due to a lot of failure cases during robotic surgery processes, for example: suture breakage because of pulling action in knot-tying, slipped on a needle of grasping action or inadequate of force. In this paper, an image-based force sensing feedback system is presented. The force feedback system can provide unmistakable for the surgeon how much force they are utilizing by showing corresponding colors, which can reduce instances of surgery failure without negatively impacting the surgeon 's performance. Visual images-based were employed to watching the distance changing of plasticity sensor during the time it was suffering an opposite reaction force from grasping action of a surgery robot arm. From the experiments, this visual images-based evaluation method can detect a minimum force value of 0.01 Newton. This system provides extraordinary accuracy of force sensing feedback and also hands controlling for a robot arm, due to the accuracy shows up to 99.96% (hands action recognition). The main distribution of this studying is to give robot-arm can use the proposed technique to estimate and utilize force values for surgical operation.

Due to the high integration required for system application, the three-dimensional chip may resolve this requirement. The three-dimensional vertically stacking (3D-stacking) systems have been proposed to satisfy these requirements. However, the 3D-stacking system contains several design risks from its long layer interconnections. For a 3D-stacking system, it is difficult to identify where the numerous power and signal-interconnection are open-, shorted-fault, or resistive-short has accrued. Therefore, solving these interconnection problems is necessary. A feasible interconnection quality-evaluation, fault-diagnosis, and connection-reconfigurable mechanism are proposed. The proposed interconnection-measurement-recovery (IMR) mechanism will make it easy to find interconnection faults and make recovery in 3D-Stacking systems. The proposed IMR can detect interconnection open, short, bridge and resistive defects with the path-reroute mechanism. Future more, the signal transmission quality can be measured. This measurement provides to monitor signal propagation in pico-second accuracy. IMR has less extra area and power consumption overhead. The feasibilities of the proposed mechanism have been justified by 2D-chip and 3D-stacking MorPack both systems.

It is accepted that advanced driver assistance systems (ADAS) play a vital role in self-driving vehicles nowadays. It consists of many devices such as Light Detection and Ranging (LIDAR) systems, distance sensors and cameras. The LIDAR becomes one of the key sensors for the distance perception of a car. This paper aims at using a single-beam LIDAR device to build a 3-dimensional (3D)-map for the vision of the self-driving portable car for rescuing applications, especially for tunnels accidents. The proposed system relies on the laser beam in the LIDAR was used to measure the distance of an object, and a 3D-map was created from distance information. The main purpose of this study was to improve the operation speed of the LIDAR system by hardware and software. In our experiments, the performance of our LIDAR was investigated with different configurations in hardware connection. The 3D-mapping technique will provide a new view of an automatic car in rescue missions.

Virtual-Reality (VR), Augmented-Reality (AR) and Mixed-Reality (MR) are finding new applications in clinical investigations. This study uses VR, AR, and MR techniques for pre-surgery applications on three platforms: Windows PC, Apple iPad, and Mobile. Using the proposed technique, which involves the use of virtual reality, augmented reality, and mixed reality technologies, a physician can visualize the problem and discuss options with a patient while the patient's anatomy is being studied. The combination of endoscopic visualization can be used for surgical planning, training, medical diagnosis, and postoperative examination.

A built-in digitalized power management (DPMM) and voltage domain programmable (VDP) mechanisms are proposed to design a low-power system. In the proposed techniques, the high and low voltages applied to logic modules can be switchable. This flexible voltage-domain assignment allows the chip performance and power consumption can dynamically adjust during circuit operation. To support the DPMM and VDP mechanisms, the voltage-level monitor circuit and power-switch circuit are designed to support multiple operation modes for DPMM-VDP digital circuit designs. A powerless retention flip-flop is developed for temporary data storage during voltage domain dynamically switching. While to prevent the system failure come from voltage integrity problem, a built-in voltage-level monitoring mechanism is utilized to monitor voltage integrity during VDP circuit operation. The proposed mechanism allows the chip performance and power consumption to be flexibly adjusted during circuit operation. The physical implementation chips and measured results proof of this methodology has 30~55 power reduction comparisons with using single-Vdd.

A swing variable voltage technique (CK-Vdd) is proposed to reduce power consume for generic digital circuit system. The proposed CK-Vdd generates a swing variable voltage, which is different from the conventional constant voltage (Vdd) to the digital circuit. The swing voltage is produced from using Voltage Frequency Adjustor (VFA) and Frequency Duty-Cycle Adjustor (FDCA) circuits. The clock rising and falling signals fanin FDCA to generate an adjustable high-low signal to control VFA generates high-low cycling swing voltage. When the clock is at positive-level, a generic positive-edge digital circuit will need large operation current. CK-Vdd supply high-voltage to the digital circuit at this time. On the other hand, when the clock signal transfers to the low-level, CK-Vdd can supply low-voltage to reduce power consumption. From reducing the supply current to the digital circuit at low-level clock, the digital circuit power consumption can be reduced. We implement the CK-Vdd technique in a H.264 video decoder test chip based on TSMC 90 nm CMOS process. The result shows that when CK-Vdd voltage is 0.7v ~ 0.9v it can save average 32% power consumption. To the maximum, decoder chip can save as high as 45% power consumption.

Minimally Invasive Surgery (MIS) is a current major surgery technique. A chief problem with MIS is its narrow field of vision. A wireless MIS Panoramic Endoscope (WMISPE) is developed and implemented to provide doctors with broad fields of view. A WMISPE features a combination of video overlapping and video stitching. The panoramic video apparatus has two side-by-side endoscopic lenses that provide wide-angle inputs for video stitching. A WMISPE can provide doctors with panoramic videos, so that they can easily discriminate an organ's position between surgical operations. Experimental results show that WMISPE can enhance the video size to 158%. A low-power multi-mode video decoder (MMVD) is used to validate the stitching videos. The whole system is validated by personal computer, an embedded system, and an H.264 decoder chip. The test chip is successfully validated after system integration, and obtains about a 24% reduction in power consumption, which is better than that of the same design using a single supply voltage. The animal vivo experimental videos have been successfully validated.

It has been proposed that small amounts of energy dissipate when transfer through a rising Vdd. In typical power gate circuits, the PMOS transistors (P SW ) reduce the leakage of power by shutting off outer Vdd to the idle blocks. We expand this technique by utilizing active P SW , which are turned on and off by a clock signal. The proposed SCKVdd technique combines the power source gated mechanism and clock signal to generate stable progressive rising voltage to suppress peak and average currents effectively. The SCKVdd technique is a scalable, clock-controlled, self-stabilized voltage technique. This technique is easily implemented in generic digital circuits to reduce power dissipation. A normal CMOS circuit shows a dynamic power consumption increase proportional to the clock frequency. SCKVdd results in a lower-than-usual frequency dependency, and is suitable for high speed clock circuits. SCKVdd can be integrated with frequency, voltage scaling and an activated P SW number to implement an efficient power-performance trade-off mechanism. In experiments that investigated constant Vdd for MPEG VLD chips, power dissipation savings were in the range of 42% to 54% with only a small delay penalty.

Minimally Invasive Surgery (MIS) is a current major technique for surgery. Compared to traditional methods of surgery, MIS can reduce the post-surgical recovery time, cost and pain to patients due to surgery. It is therefore in the interest of doctors and patients. There are several MIS techniques that have been widely accepted for diagnosis and treatment in most hospitals, such as hysteroscopy, laparoscopy, and colon endoscopy. The major problem of MIS is a narrow field of vision. We develop and validate a MIS Panoramic Endoscope (MISPE) to provide doctors with broad fields of view. MISPE features a combination of image overlapping and image stitching. The panoramic image apparatus has two side-by-side endoscopic lenses that provide wide-angle inputs for image stitching. MISPE can provide doctors with panoramic images, so that doctors can easily discriminate the organ's positions between surgery operations. Experimental results show that MISPE can enhance the image size up to 155%. The whole system is validated by personal computer. The animal vivo experimental videos have been successfully validated.

The proposed low-cost, scalable, synthesizable Voltage-Frequency Adjustor (VFA) design provides voltage and frequency automatic adjustments for implementing low-power systems. This design is effective in reducing power consumption from managing the supplied current and clock frequency for the structurally dynamic varying systems. The VFA supplied electrical current amount and voltage level are automatically adjusted from sensing the voltage drop of the fanout load. This adjustment mechanism controls the activated power switch quantity to allow a structure varied design that can obtain a stable fanin voltage level, regardless of the designed module that is dynamically added or removed from the system. Compared to the conventional dynamic voltage frequency scaling technique, the VFA is cost effective and can be easily integrated with the target design as a single chip. The experimental results show that the combination of VFA chips and an H.264 video decoder is successfully validated with 49%~68% power reduction compared to the case that the H.264 video decoder directly uses an outer power supply.

This paper proposes a dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width. A design automation environment for simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 um CMOS technology, it comprises 439Kgates/10.9KB SRAM and consumes 2~328mW in decoding CIF~HD1080 videos at 3.75~30fps when operating at 1~150MHz, respectively.

The high speed dual phase operation domino circuit, which includes high-performance and reliable characteristics is proposed, and the circuit design technique with practical implementation is presented. The cell-based automatic synthesis flow supports the quick design of high performance chips. The test chip of a dual-phase 64 bit high-speed multiplier with a built-in performance adjustment mechanism is successfully validated using TSMC 0.18 technology. The test chip shows ×2.7 performance improvement compared to the conventional static CMOS logic design.

Exploiting a charge sharing method enables a performance power management design for domino circuits. The domino circuits have both high performance and low power consumption. A test chip has been successfully validated using TSMC 0.13um CMOS technology. Reductions in dynamic power consumption of 68% and static power consumption of 15% are achieved.

At speed Built-In Self Test (BIST) circuit can solve many test challenges generated from traditionally slower Automatic Test Equipment (ATE). In this paper, a double edge clipping technique is proposed for built-in at-speed delay testing requirements. It differs from traditional circuit delay testing techniques by changing the clock rate using external ATE. This method uses lower-speed input clock frequency, then applies internal BIST technique to adjust clock edges for circuit at-speed delay testing and speed binning. Test chips are fully validated. The fine-scale (16ps) progressive capture edge adjustment technique with high-precision (28ps) calibration circuit is effective for at-speed delay testing and performance binning.

An at-speed BIST delay testing technique is proposed. It differs from traditional circuit speed testing techniques by changing the system clock rate. This method supplies test pattern to the circuit using lower-speed clock frequency, then applies internal BIST circuit to adjust clock edge for circuit at-speed delay testing and speed binning. The self wide-range (26%∼76%), fine-scale (34ps) duty cycle adjustment technique with high-precision (28ps) calibration circuit is proposed for at-speed delay test and performance binning. The contribution of this work is the proposal of a feasible self at-speed delay testing technique. Test chip DFT strategies are fully validated by instruments and HOY wireless test system.

Multi-voltage technique is an effective way to reduce power consumption. In the proposed voltage domain programmable (VDP) technique, high and low voltage domains applied to logic gates are programmable. The different voltage domains allow the chip performance and power consumption to be flexibly adjusted during circuit operation. In this proposed internal of the chip technique, the power switches possess the feature of flexible programming after chip manufacturing. The video decoder test chip proof of this novel methodology has 55% power reduction with good power-performance management mechanism.

Delay testing has become a major issue for manufacturing advanced Systems on a Chip. Automatic Test Equipment and scan techniques are usually applied in delay testing. However, the circuits under test have many circuit paths and dependent input patterns; it is hard to measure delay times accurately, especially when debugging small delay defects. We propose a Built-In Delay Measurement (BIDM) circuit that is modified from Vernier Delay Lines. All digitally designed BIDMs with small area overhead can be easily embedded within testing circuits. BIDMs can be used to record the data propagation delay times within circuit path segments, for delay testing, diagnosis, and calibration requirements internal to the chip. Our BIDM was implemented in a 32 bit error correction circuit by a chip using TSMC 0.18u technology. The instruments measured results showing that the BIDM chip correctly reported the CUT segment path delay times. The chip measurement results were a 95.83% match to the postlayout SPICE simulation values. This BIDM makes it possible to debug small delay defects in chips.

We propose a self-stabilized ramp voltage technique, CKVdd, to reduce power dissipation in conventional CMOS circuit. Normal CMOS circuits show a power increase proportional to clock frequency. CKVdd results in a lower-than-usual power increase. This technique is easily implemented in CMOS circuits. CKVdd technique possesses several characteristics that differ from of the current circuits using Vdd power source. First, CKVdd circuits have less average current and peak current consumption, such that it can be a low power design technique applied to generic digital circuits. Second, CKVdd technique combines the power source and clock signal, and can easily implement the power management mechanism. Compared to constant Vdd for multimedia decoders, the proposed technique has 45% of the usual power dissipation and 88% of the usual peak current reduction at the cost of small delay penalty.

The self wide-range (26%~76%), fine-scale (34 ps) duty cycle adjustment technique with high-precision (28 ps) calibration circuit are proposed for at-speed delay test and performance binning. Test chip DFT strategies are validated fully function work by instruments and HOY wireless test system.

Through reducing 70% of external memory bandwidth and 60% of computational complexity, the proposed 252 Kgates/71 mW/0.13 um multi-standard (JPEG/MPEG-1/2/4/H.264) video decoder reduces 72% in gate count and 87% in power consumption as compared to the state-of-the-art design, when operating at 120 MHz for real-time HD1080 video decoding with single AHB-based SDR memory.

A double edge clipping technique is proposed for at-speed BIST testing. It differs from traditional circuit delay testing techniques by changing the clock rate using external ATE. This method uses lower-speed input clock frequency, then applies internal BIST circuit to adjust clock edges for circuit at-speed delay testing and speed binning. This built-in at-speed delay test with calibration mechanism named as double edge clipping (DEC) technique. DEC is based on the lunch on shift (LOC) scheme by precisely controlling the launch and capture edges during delay test operation. Two wide-range (26% -80%), fine-scale (16ps) duty cycle adjustment circuits with high-precision (28ps) calibration mechanism are effective applied for at-speed delay testing and performance binning. The key to DEC testing technique is to generate a pair of clock pulses for the launch and capture events. Two DCPG provide adjusted positive clock edge during test operation. DEC uses 500kHz low speed input clock then provides working clock frequency from 197MHz to 932MHz.

This article proposes a low-cost, low-power multistandard video decoder for high definition (HD) video applications. The proposed design supports multiple-standard (JPEG baseline, MPEG-1/2/4 Simple Profile (SP), and H.264 Baseline Profile (BP)) video decoding through interactive parsing control and common parameter bus interface. In order to reduce hardware cost, the shared adder-based structure and reusable data management are proposed to achieve hardware sharing and reduce internal memory size, respectively. In addition, the proposed design is optimized through reducing memory bandwidth by increasing both data reuse amount and burst length of memory access as well as eliminating cycle overhead in data access for supporting HD video decoding with single AHB-based SDR memory. The proposed 252Kgates/4.9kB/71mW/0.13μm multi-standard video decoder reduces 72% in gate count and 87% in power consumption as compared to the state-of-the-art design, when operating at 120MHz for real-time HD1080 video decoding with single AHB-based SDR memory.

Delay testing has become a major issue for manufacturing advanced systems on a chip. Automatic test equipment and scan techniques are usually applied in delay testing. However, the circuits under test have many circuit paths and dependent input patterns; it is hard to measure delay times accurately, especially when debugging small delay defects. We propose a built-in delay measurement (BIDM) circuit that is modified from Vernier delay lines. All digitally designed BIDMs with small area overhead can be easily embedded within testing circuits. BIDMs can be used to record the data propagation delay times within circuit path segments, for delay testing, diagnosis, and calibration requirements internal to the chip. Our BIDM was implemented in a 32bit error correction circuit by a chip using TSMC 0.18u technology. The instruments measured results showing that the BIDM chip correctly reported the CUT segment path delay times. The chip measurement results were a 95.83% match to the postlayout SPICE simulation values. This BIDM makes it possible to debug small delay defects in chips.

As device size continues to shrink in the sub-micron regime, power supply noise is becoming a performance and reliability bottleneck in modern VLSI design. In this paper, we propose a new floorplanning methodology for fast power supply noise design convergence. By evaluating power supply noise at this early design stage, area-efficient floorplans with considering IR voltage drop and electromigration (EM) are generated. Compared to designs based on area-optimized floorplans, the proposed methodology achieves noise-satisfied designs with an average 52% less power routing resource.

Power-gate is a well-known technology used to decrease static (leakage) power consumption in low-power circuit currently. Several PMOS transistors are used as power switches (p-switches) to control the power source within the power-gating circuit. The p-switches are attached between the Vdd and the virtual Vdd power rail which served as the power source of circuit. The system of power management unit will turn off the power supply of the idle core by switching off the p-switches. As we know, the performance of a circuit depends on whether the supplied current is sufficient or not, and it relies on how much the channel width of p-switches could turn on simultaneously. Some defects will make the p-switches channel width diminished. The phenomenon of reducing channel width will not only affect the circuit performance but also cause chip reliability degrades because the current flow of p-switches overloaded. Therefore, it is important to diagnose/test the failed/defective p-switches. In this paper, the proposed CKVdd technique could easily identify the performance degradation caused by the failed/defective p-switches within the power-gating circuit.

Charge sharing, which occurs in any complementary metal-oxide-semiconductor (CMOS) domino gate, may degrade the output voltage level or may even cause an erroneous output value. In this paper, this problem is thoroughly investigated by considering circuit topology and circuit function. We describe a method to measure the sensitivity [called charge-sharing (CS) vulnerability] of the CS problem for each domino gate. A method to derive the CS vulnerability and the test vector for each domino gate is suggested. We also propose a transistor reordering method to dramatically reduce the CS vulnerabilities for all domino gates so that the CS problem can be alleviated. We also prove theoretically that a set of test vectors generated for single charge-sharing faults (SCSFs) can also detect all multiple charge-sharing faults (MCSFs). This good property significantly guarantees the test quality for the CS faults of domino circuits.

Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor. However, domino logic suffers from several problems and one of the most notable ones is the charge sharing problem. In this paper, we describe a method to measure the sensitivity of the charge-sharing problem for each domino gate. In addition, our algorithm also generates test vectors to detect the worst case of charge-sharing fault.

The purpose of a testability analysis program is to estimate the difficulty of testing a fault. A good measurement can give an early warning about the testing problem so as to provide guidance in improving the testability of a circuit. There have been researches attempting to efficiently compute the testability analysis. Among those, the Controllability and Observability Procedure COP (1984) can calculate the testability value of a stuck-at fault efficiently in a tree-structured circuit but may be very inaccurate for a general circuit. The inaccuracy in COP is due to the ignorance of signal correlations. The algorithm of TAIR (Testability Analysis by Implication Reasoning) proposes a testability analysis algorithm, which starts from the result of COP and then gradually improves the result by applying a set of rules. The set of rules in TAIR can capture some signal correlations and therefore the results of TAIR are more accurate than COP. In this paper, we first prove that the rules in TAIR can be replaced by a closed-form formulation. Then, based on the closed-form formulation, we proposed two novel techniques to further improve the testability analysis results. Our experimental results have shown improvement over the results of TAIR.

The Charge Sharing (CS) problem is one of notorious noise problems in domino circuits design and test. In this paper, this problem is thoroughly investigated by considering circuit topology and circuit function. The sensitivity of each domino gate to the CS problem is represented by the concept of CS-vulnerability. A method to derive the CS-vulnerability and the test pattern for each domino gate is suggested. We also propose a transition reordering method to dramatically reduce the CS-vulnerabilities for all domino gates, so that the CS problem can be alleviated. Simulation results demonstrate that our transistor reordering method can efficiently reduce the CS-vulnerabilities for most of domino circuits.

This paper presents an effective reconfiguration scheme consisting of detailed spare replacement, processor placement, routing, and switch programming mechanisms. A new switch programming scheme is proposed to reduce the hardware overhead of reconfiguration. A thorough yield simulation tool has been developed for accurate prediction of yield by considering the effects of defect clusters and switching network failures. This yield simulation tool can also be used to obtain the information on the performance degradation, spare replacement, processor placement, routing and the switch programming algorithm survival probability.