Many parallel SystemC approaches expect a thread safe and conflict free model from the designer. Alternatively, an advanced compiler can identify and avoid possible parallel access conflicts. While manual conflict resolution can theoretically be more precise, it is impractical for real world applications because of the inherent complexities. Here automatic compiler-based analysis is preferred which provides conservative conflict avoidance with minimal false positives. This paper introduces a novel compiler technique called Port Call Path analysis that greatly reduces the amount of false positive conflicts resulting in significantly increased simulation speed. Experimental results show that the new analysis reduces the amount of false conflicts by up to 98% and, on a 4-core processor, speeds up the simulation up to 3× for a NoC particle simulator and 3.5× for a bitcoin miner SystemC model.

IEEE SystemC is one of the most popular standards for system level design. With the Recoding Infrastructure for SystemC (RISC), a SystemC model can be executed at segment level in parallel. Although the parallel simulation is generally faster than its sequential counterpart, any data conflict among segments reduces the simulation speed significantly. In this paper, we propose for RISC users a coding guideline that increases the granularity of segments, so that the level of parallelism in the design increases and higher simulation speed becomes possible. Our experimental results show that a maximum speedup of over 6.0x is achieved on an 8-core processor, which is 1.7 times faster than parallel simulation without the coding guideline.

Parallel SystemC approaches expect a thread-safe and race-condition-free model from the designer or use a compiler which identifies the race conditions. However, they have strong limitations for real world examples. Two major obstacles remain: a) all the source code must be available and b) the entire design must be statically analyzable. In this paper, we propose a solution for a fast and fully accurate parallel SystemC simulation which overcomes these two obstacles a) and b). We propose a hybrid approach which includes both static and dynamic analysis of the design model. We also handle library calls in the compiler analysis where the source code of the library functions is not available. Our experiments demonstrate a 100% accurate execution and a speedup of 6.39× for a Network-on-Chip particle simulator.

Most parallel SystemC approaches have two limitations: (a) the user must manually separate all parallel threads to avoid data corruption due to race conditions, and (b) available hardware vector units are not utilized. In this paper, we present an advanced compiler infrastructure for automatic parallelization of SystemC models at the thread-level. In addition, our infrastructure exploits opportunities for data-level parallelization. Our experimental results show a nearly linear speedup of NxM, where N and M denote the thread and data-level factors, respectively. In turn, a 4-core multi-processor achieves a speedup of up to 8.8x, and a 60-core Xeon Phi processor reaches up to 212x.

In an ideal top-down system design flow, graphical diagrams are designed before an executable specification in a System Level Description Language (SLDL) is derived. Such initial charts typically also serve as visual documentation of the textual specification and aid in maintaining the model. In the absence of graphical charts, e.g. in case of legacy or 3rd party code, a textual SLDL model is hard to comprehend for any unfamiliar designer. Here, we propose to automatically extract graphical charts from given SystemC code to ease the understanding of the source code with a visual representation. Specifically, we extract the communication flow between the threads from the design model by use of an automatic SystemC compiler infrastructure that statically analyzes the code and generates custom Thread Communication Graphs (TCG) similar to message sequence charts. Our experimental results on embedded applications demonstrate that our novel static analysis can quickly extract accurate TCG that are highly useful for designers in becoming familiar with new source code.

With the increasing demand for parallel computing power, manycore platforms are attracting more and more attention due to their potential to improve performance and scalability of parallel applications. However, as the core count increases, core-to-core communication becomes expensive. For manycore architectures using directory-based cache coherence protocols, the core-to-core communication latency depends not only on the physical placement on the chip, but also on the location of the distributed cache tag directory. In this paper, we first define the concept of core distance for multicore and manycore architectures. Using a ping-pong spin-lock benchmark, we quantify the core distance on a ring-network platform and propose an approach to optimize thread-to-core mapping in order to minimize on-chip communication overhead. In our experiments, our approach speeds up communication-intensive benchmarks by more than 25% on average over the Linux default mapping strategy.

We introduce the level-ordered edge sequence (LOES), a suc- cinct encoding for state-sets based on prefix-trees. For use in state-space search, we give algorithms for member testing and element hashing with runtime dependent only on state- size, as well as space and memory efficient construction of and iteration over such sets. Finally we compare LOES to binary decision diagrams (BDDs) and explicitly packed set- representation over a range of IPC planning problems. Our results show LOES produces succinct set-encodings for a wider range of planning problems than both BDDs and ex- plicit state representation, increasing the number of problems that can be solved cost-optimally.

In this paper we describe novel representations for precomputed heuristics based on Level-Ordered Edge Sequence (LOES) encodings. We introduce compressed LOES, an extension to LOES that enables more aggressive compression of the state-set representation. We evaluate the novel repre- sentations against the respective perfect-hash and binary decision diagram (BDD) representations of pattern databases in a variety of STRIPS domains.

We show how edge partitioning, a technique originally developed for external-memory search, can be used to reduce the number of slow synchronization operations needed in parallel graph search. We show that edge partitioning improves on a previous technique called parallel structured duplicate detection by allowing a higher degree of concurrency, even for search problems with little or no inherent locality. For domain-independent graph search, we also show that edge partitioning significantly improves search speed by improving the efficiency of precondition checking. We demonstrate the effectiveness of this approach to parallel graph search for domain-independent STRIPS planning.

In model-based production, a planner uses a system description to create plans that achieve production goals. The same description can be used by model-based diagnosis to infer the condition of components from sensor data. When production is realized by a sequence of plans, prior work has demonstrated that diagnosis can be used to adapt the plans to compensate for component degradation. However, the sources of diagnostic information are severely limited. Diagnosis must either make inferences from observations during production over which it has no control (passive diagnosis), or production must be halted to introduce diagnostic-specific plans (explicit diagnosis). We observe that the declarative nature of the model-based approach allows the planner to achieve production goals in multiple ways. This flexibility is exploited by a novel paradigm, i.e.,pervasive (active) diagnosis, which constructsinformative production plansthat simultaneously achieve production goals while uncovering additional diagnostic information about the condition of components. We present an efficient heuristic search for these informative production plans and show through experiments on a model of an industrial digital printing press that the theoretical increase in long-run productivity can be realized on practical real-time systems. We obtain higher long-run productivity than a decoupled combination of planning and diagnosis.

We present an original graph embedding to speedup distance-range andk-nearest neighbor queries on static and/or dynamic objects located on a (weighted) graph. Our method is used to compute a lower and upper bounding filter distance which approximates the true shortest path distance significantly better than traditional filters. In addition, we discuss how the computation of the exact shortest path distance in the refinement step can be boosted by using the embedded graph.

In this paper, we present an original network graph embedding to speed-up distance-range and k-nearest neighbor queries in (weighted) graphs. Our approach implements the paradigm of filter-refinement query processing and can be used for proximity queries on both static as well as dynamic objects. In particular, we present how our embedding can be used to compute a lower and upper bounding filter distance which approximates the true shortest path distance significantly better than traditional filters, e.g. the Euclidean distance. These distance approximations can be used within a filter step to prune true drops and true hits as well as in the refinement step in order to guide an informed A* search. Our experimental evaluation on several real-world data sets demonstrates a significant performance boosting of our proposed concepts over existing work.

We describe our approach of developing AR applications with expressive visual representations and realistic object behavior. We combine concepts from high-level scene graphs, physical simulation libraries and a Java binding for ARToolkit with the ideas of iterative prototyping and show that rapid development of expressive AR applications using Java is possible.