This paper presents a mixed-signal Silicon Photomultiplier with integrated front-end, including a reconfigurable Pulse Shaper. Each Silicon Photon Avalanche Diode of the msSiPM converts a photon into a programmable current pulse. Then, all analog current signals are collected by a transimpedance amplifier which provides an output voltage proportional to the number of triggered SPADs. By properly tuning the shape of the current pulses, the proposed msSiPM rejects the background light and optimizes the Signal-to-Noise Ratio. As the architecture is mostly digital, msSiPM consumes a low static power consumption, equal to 428$\mu $W. The receiver is composed by a$20 \,\, \times 20$-pixel array, and it is fabricated in a 0.11$\mu $m CMOS technology reaching a pixel fill factor equal to 32.8%. Measurements have been carried out under different background photon fluxes, one stronger and one weaker, corresponding to 4.15 and 2.15 GPhotons/s at the SiPM, demonstrating strong background rejection in both conditions. In addition, a SNR maximization has been verified. Analytical models for SNR and Signal-to-Background Ratio have been presented, showing a good matching with experimental results.

In this study, we examine the potential of using high-resolution satellite imagery and machine learning techniques to create income maps with a high level of geographic detail. We trained a convolutional neural network with satellite images from the Metropolitan Area of Buenos Aires (Argentina) and 2010 census data to estimate per capita income at a 50x50 meter resolution for 2013, 2018, and 2022. This outperformed the resolution and frequency of available census information. Based on the MobileNetV3 architecture, the model achieved high accuracy in predicting household incomes (R2= 0.77), surpassing the spatial resolution and model performance of other methods used in the existing literature. This approach presents new opportunities for the generation of highly disaggregated data, enabling the assessment of public policies at a local scale, providing tools for better targeting of social programs, and reducing the information gap in areas where data is not collected.

We describe the implementation in a self-standing system of a novel contrast-based binary CMOS imaging sensor.This sensor is characterized by very low power consumption and wide dynamic range, which makes it attractive for wireless camera network applications. In our implementation,the sensor is interfaced with a Flash-based FPGA processor,which handles data readout and image processing.This self-standing camera node is configured as a system for counting persons walking through a corridor. Simple features are extracted from each image in a video stream at 30 fps. A classifier is designed based on the temporal evolution of these features, which is modeled as a Markov chain. The video stream is then segmented into intervals corresponding to individual persons crossing through the field of view. Experimental results are shown in cross-validated tests over real sequences acquired by the camera.

The presented demonstrator implements a person counting system using a single overhead sensor and counting the number of people going in and out of an observed area. It is based on a low-power vision sensor, which extracts the contrast of the image in a binary form, implements motion by differencing two successive frames and dispatches the asserted pixels through an address-driven data representation. A lightweight counting people algorithm has been developed, which is based on virtual loop. The demonstrator consists of the vision sensor interfaced with the FPGA and linked to a PC with a graphical interface.

The presented demonstrator is capable of detecting a user-defined amount of motion in a scene with a limited energy-budget. This makes it suitable to be used as an energy- autonomous vision sensor for a wireless sensor network. It consists of a low-power contrast-based CMOS vision sensor interfaced with an FPGA and linked to a PC through the USB. The low-power vision sensor directly extracts the visual contrast of images in binary form and estimates the motion in the scene through a temporal matching, without dispatching any pixel outside the chip. The amount of moving pixels between two successive frames is computed by the sensor and compared outside the chip, with respect the a user-programmed value, by means of the FPGA, This low-power operating mode takes about 60 muW at a frame rate of 50 fps and does not occupy any data bandwidth.