Article Probabilistic CTSS: analysis of timing error probability in asynchronous logic circuits Share on Authors: Yutaka Deguchi Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, Japan Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, JapanView Profile , Nagisa Ishiura Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, Japan Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, JapanView Profile , Shuzo Yajima Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, Japan Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, JapanView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 650–655https://doi.org/10.1145/127601.127745Published:01 June 1991 7citation160DownloadsMetricsTotal Citations7Total Downloads160Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

In this paper we propose a new timing verification technique named coded time-symbolic simulation, CTSS. We are concerned with simulation of logic circuits consisting of gates whose delay is specified only by its minimum and maximum values. We encode the cases of possible delay values of each gate by binary values and simulate all the possible combinations of the delay values by means of symbolic simulation. This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits. We implemented an efficient simulator by using a shared binary decision diagram (SBDD) as an internal representation of Boolean functions. We also propose novel techniques of analyzing the results of CTSS.