The Network-on-Chip (NoC) paradigm has emerged as a revolutionary methodology for integrating a very high number of intellectual property (IP) blocks in a single die. The achievable performance benefit arising out of adopting NoCs is constrained by the performance limitation imposed by the metal wire, which is the physical realization of communication channels. With technology scaling, only depending on the material innovation will extend the lifetime of conventional interconnect systems a few technology generations. According to International Technology Roadmap for Semiconductors (ITRS) for the longer term, new interconnect paradigms are in need. The conventional two dimensional (2D) integrated circuit (IC) has limited floor-planning choices, and consequently it limits the performance enhancements arising out of NoC architectures. Three dimensional (3D) ICs are capable of achieving better performance, functionality, and packaging density compared to more traditional planar ICs. On the other hand, NoC is an enabling solution for integrating large numbers of embedded cores in a single die. 3D NoC architectures combine the benefits of these two new domains to offer an unprecedented performance gain. In this paper we evaluate the performance of 3D NoC architectures and demonstrate their superior functionality in terms of throughput, latency, energy dissipation and wiring area overhead compared to traditional 2D implementations.

Three dimensional (3D) network on chip (NoC) has attracted researchers' attention recently. 3D NoCs are capable of achieving better system throughput and lower latency compared to the corresponding 2D implementations. To fully exploit the performance benefits of 3D architectures, it is imperative to address signal integrity issues in the design phase and its implications on energy dissipation. In this work we show that by incorporating joint crosstalk avoidance and multiple error correction schemes it is possible to enhance the robustness and reduce the energy dissipation simultaneously for both the 3D and more conventional planar NoC architectures. The achievable energy savings in 3D NoCs is significantly more than that in 2D structures.