The end of Moore's law has been proclaimed on many occasions and it's probably safe to say that we are now working in the post-Moore era. But no one is ready to slow down just yet. We can view Gordon Moore's observation on transistor densification as just one aspect of a longer-term underlying technological trend - the Law of Accelerating Returns articulated by Kurzweil. Arguably, companies became somewhat complacent in the Moore era, happy to settle for the gains brought by each new process node. Although we can expect scaling to continue, albeit at a slower pace, the end of Moore's Law delivers a stronger incentive to push other trends harder. Some exciting new technologies are now emerging such as multi-chip 3D integration and the introduction of new technologies such as storage-class memory and silicon photonics. Moreover, we are also entering a golden age of computer architecture innovation. One of the key drivers is the pursuit of domain-specific architectures as proclaimed by Turing award winners John Hennessy and David Patterson. A good example is the Xilinx's AI Engine, one of the important features of the Versal? ACAP (adaptive compute acceleration platform). Today, the explosion of AI workloads is one of the most powerful drivers shifting our attention to find faster ways of moving data into, across, and out of accelerators. Features such as massive parallel processing elements, the use of domain specific accelerators, the dense interconnect between distributed on-chip memories and processing elements, are examples of the ways chip makers are looking beyond scaling to achieve next-generation performance gains.

The end of Moore's law has been proclaimed on many occasions and it's probably safe to say that we are now working in the post-Moore era. But no one is ready to slow down just yet. We can view Gordon Moore's observation on transistor densification as just one aspect of a longer-term underlying technological trend - the Law of Accelerating Returns articulated by Kurzweil. Arguably, companies became somewhat complacent in the Moore era, happy to settle for the gains brought by each new process node. Although we can expect scaling to continue, albeit at a slower pace, the end of Moore's Law delivers a stronger incentive to push other trends of technology progress harder. Some exciting new technologies are now emerging such as multi-chip 3D integration and the introduction of new technologies such as storage-class memory and silicon photonics. Moreover, we are also entering a golden age of computer architecture innovation. One of the key drivers is the pursuit of domain-specific architectures as proclaimed by Turing award winners John Hennessy and David Patterson. A good example is the Xilinx's AI Engine, one of the important features of the Versal? ACAP (adaptive compute acceleration platform) [1]. Today, the explosion of AI workloads is one of the most powerful drivers shifting our attention to find faster ways of moving data into, across, and out of accelerators. Features such as massive parallel processing elements, the use of domain specific accelerators, the dense interconnect between distributed on-chip memories and processing elements, are examples of the ways chip makers are looking beyond scaling to achieve next-generation performance gains. Next, the growing demands of scaling-out hyperscale datacenter applications drive much of the new architecture developments. Given a high diversification of workloads that invoke massive compute and data movement, datacenter architectures are moving away from rigid CPU-centric structures and instead prioritize adaptability and configurability to optimize resources such as memory and connectivity of accelerators assigned to individual workloads. There is no longer a single figure of merit. It's not all about Tera-OPS. Other metrics such as transfers-per-second and latency come to the fore as demands become more real-time; autonomous vehicles being an obvious and important example. Moreover, the transition to 5G will result in solutions that operate across the traditional boundaries between the cloud and edge and embedded platforms that are obviously power-conscious and cost-sensitive. Future workloads will require agile software flows that accommodate the spread of functions across edge and cloud. Another industry megatrend that will drive technology requirements especially in encryption, data storage and communication, is Blockchain. To some, it may already have a bad reputation, tarnished by association with the anarchy of cryptocurrency, but it will be more widely relevant than many of us realize. Who could have foreseen the development of today's Internet when ARPANET first appeared as a simple platform for distributed computing and sending email? Through projects such as the open-source Hyperledger, Blockchain technology could be game-changing as a platform for building trust in transactions executed over the Internet. We may soon be talking in terms of the Trusted Internet. The predictability of Moore's law may have become rather too comfortable and slow. The future requires maximizing the flexibility, agility, and efficiency of new technologies. With Moore's Law now mostly behind us, new adaptable and scalable architectures will allow us to further provide exponential return from technology in order to create a more adaptable and intelligent world.

Provides an abstract for each of the 4 keynote presentations and may include a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.

Since their inception, FPGAs have changed significantly in their capacity and architecture. The devices we use today are called upon to solve problems in mixed-signal, high-speed communications, signal processing and compute acceleration that early devices could not address. The architecture has evolved towards an "All Programmable" platform that immerses multiple programmable technologies into a complex interconnect infrastructure that, today, spans the boundary of multiple dies in one package. As the devices continue to grow in capability and complexity, new design tools and methodologies are being proposed. We will discuss future technology challenges that need to be solved in order to continue pushing the boundary of integration.

These keynote speeches the following: All Programmable SOC FPGA for Networking and Computing in Big Data Infrastructure; Designing Analog Functions without Analog Transistors; Beyond Charge-Based Computing; The Art of Innovation - How Singapore Will Continue to Drive the Progress in Semiconductor Technologies.

Summary form only given: Modern FPGA platforms have capabilities that are well suited to assume a more central role in the implementation of complex embedded processing systems. The aggressive adoption of Moore's Law and the application of emerging 3D stacked silicon interconnect technology have resulted in the growth of FPGA capacity that outperforms Moore's Law. In particular, FPGAs are well placed to be at the heart of complex signal processing, packet processing and high performance computing applications because of their high computational efficiency matched by high bandwidth concurrent memory access and rich on-chip interconnectivity, all of this combined with complete programmability and best in industry power efficiency. The key to unleashing the full horsepower of FPGA platforms to the system designer is, first of all, a hardware platform that allows tight integration between the processor, the programmable logic and the memory. Second, the hardware architecture has to be supported by a programming flow that abstracts the hardware implementation details and provides seamless and efficient mapping of system functions on multiple processor cores and programmable hardware functions. Finally, a programmable infrastructure has to be provided that targets specific requirements for packet processing or signal processing or high performance computing.

CPUs are multicore (and multi-cache) supported by a coherent, global, shared memory model. FPGAs offer a vast number of distributed programmable function blocks and distributed memory blocks across distributed memory spaces. This presentation will discuss a hybrid computing architecture that unifies the development of applications for a combined CPU-FPGA platform. The proposed programming model is based on message passing (MPI) and distributed memory. NoCs are at the heart of the hybrid platform managing the control and data flows. NoCs are implemented through shared memory buffers on the CPU portion of the hybrid computing platform. On parallel hardware, NoCs are implemented as application-specific point-to-point networks exploiting the abundant routing and switching resources of the FPGA. NoCs enable application-specific memory models while keeping with standard, familiar programming models such as MPI.

As FPGApsilas become the heart of embedded systems, the use of these programmable platforms becomes more pervasive in markets such as automotive, consumer electronics, industrial and medical. We will discuss the opportunities for FPGAs as they evolve to solve the challenges for transforming, transporting and computing data. We will describe a vision of future use models of FPGApsilas and the implications on system architectures and software environments.

Electronic system-level (ESL) design automation has been identified by Dataquest as the next productivity boost for the semiconductor industry. We have put together a distinguished panel of experts to discuss if we are ready for system-level synthesis.

Increasing design cost and risk is causing more and more designers to build configurable platforms that will amortize design and manufacturing costs across many generations. Several reconfiguration schemes exist and none of them seems to be a clear winner. Most notably there are three forms of technology: structured ASIC, configurable software programmable, reconfigurable FPGA-like platform. New solutions are emerging and may induce drastic changes in the current industry organization. The panel will examine factors in the success of the various options, and look to what the future might bring.

No abstract available.

Process technology and architecture innovation are the two engines that have fueled a spectacular advancement in FPGAs over the past 10 years. Programmable FPGA platforms give designers the benefits of deep submicron but rather than focusing on getting the silicon to work, one can focus on getting the design to work. We predict that FPGAs will become the heart of most systems over the next 5 years, replacing ASICs and processors as the fabric of choice.

The realization of new MPEG-4 functionality, applicable to three-dimensional graphics texture compression and image database access over the Internet, is demonstrated on a heterogeneous platform with several unique features. First, applying our system-level design methodologies effectively removes all data transfer and storage overhead that comprises the main bottleneck in the original system description. Second, a first-of-a-kind application specific solution, called Ozone, accelerates the embedded-zero-tree based encoding and is capable of compressing 30 color CIF images per second. The entire application is running on the Ozone coupled to a PC.

Future networked appliances should be able to download new services or upgrades from the network and execute them locally. This flexibility is typically achieved by processors that can download new software over the network, using JAVA technology. The paper demonstrates that FPGAs are a realistic implementation platform for thin server or client applications. FPGAs can offer the same end-user experience as software based systems, combined with more computational power and lower cost.

Substrate noise generated by large digital circuits degrades the performance of analog circuits sharing the same substrate. Existing approaches usually extract the model of the substrate from the layout information and then simulate the extracted transistor-level netlist with this substrate model using a transistor-level simulator. For large digital circuits, the substrate simulation is however not feasible with a transistor-level simulator. In our previous work, it has been demonstrated that efficient and accurate simulation of substrate noise generation at gate-level is feasible. In this paper several important extensions to our previous work are introduced: modeling of I/O cells, modeling of input transition time and load dependency and the extraction methodology of an equivalent substrate model within multiple supply domains. Experimental results show an improved accuracy (6.3% error on RMS substrate voltage with respect to a full SPICE level simulation) with these extensions, while maintaining a large speedup with respect to SPICE simulations.

Multicarrier modulation schemes are widely used in several digital telecommunication systems, such as Asymmetric Digital Subscriber Lines (ADSL) and Wireless Local Area Network (WLAN) based on Orthogonal Frequency Domain Multiplexing (OFDM). An estimate of the Bit-Error-Rate (BER) degradation due to non-idealities in the transceiver (e.g. nonlinear distortions in the analog front-ends, digital clipping,...) is much more complicated in a multicarrier system than in a single-carrier system due to the large number of carriers and the huge number of possible transmitted symbols. This paper proposes a method for estimating the BER of such OFDM modulation schemes in a CPU time that is two orders of magnitude smaller than a Monte-Carlo method, as confirmed by simulations on a 5 GHz IEEE 802.11 WLAN receiver front-end.

Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance degradation, the total amount of generated substrate noise must be known. Simulating substrate noise generated by large digital circuits is however not feasible with existing circuit simulators and detailed substrate models due to the long simulation times and high memory requirements. We have developed a methodology to simulate this substrate noise generation at a higher level. Not only does this methodology take noise coupling from switching gates into account, but also noise coupling from the power supply is included. This paper describes this simulation methodology. In the paper it is shown that the high-level simulations correspond very well with SPICE simulations and that a large gain in simulation speed is obtained. This high-level simulation methodology makes it possible to predict substrate noise generation of large digital circuits in a very efficient way, early in the design flow of mixed-signal ASICs.

The explosion of the telecommunications market requires miniaturization and cost-effective realization of the front-ends of transceivers for digital telecommunications. New architectures must therefore be simulated at high level. Current methodologies and corresponding tools suffer from common drawbacks, such as lower accuracy, slow simulation speed, etc. A new methodology has been developped for the efficient simulation, at the architectural level, of mixed-signal front-ends of digital telecom transceivers. The efficient execution is obtained using a multi-rate, multi-carrier signal representation together with a dataflow simulation scheme which switches dynamically towards the most efficient signal processing technique available. An implementation of this methodology shows both excellent runtimes and a high accuracy.

The design of analog front-ends of digital telecommunication transceivers requires simulations at the architectural level. The nonlinear nature of the analog front-end blocks is a complication for their modeling at the architectural level, especially when the nonlinear behavior is frequency dependent. This paper describes a method to derive a bottom-up model of nonlinear analog continuous-time circuits used in communication systems. The models take into account frequency dependence of the nonlinear behavior, making them suitable for wideband applications. Such model consists of a block diagram that corresponds to the most important contributions to the second- and third-order Volterra kernels of the output quantity (voltage or current) of a circuit. The examples in this paper, a high-level model of a CMOS low-noise amplifier and an active lowpass filter, demonstrate that the generated models can be efficiently evaluated in high-level dataflow-type simulations of mixed-signal front-ends and that they yield insight in the nonlinear behavior of the analog front-end blocks.

Future high-performance wireless communication applications such as wireless local area networks (WLANs) around 5 GHz require low-power and highly integrated transceiver solutions. The integration of the RF front end especially poses a great challenge in these applications, as traditional front-end implementations require a large number of external passive components. In this paper, we present the single-package integration of complete transceivers based on a thin-film multichip module (MCM) technology with integrated passives. The MCM substrate is a a common carrier onto which different ICs are mounted. passive components such as RF bandpass filters, inductors, capacitors, and resistors are directly integrated into the MCM substrate with the use of the multilayer structure of the MCM technology. The "system-on-a-package" approach is illustrated with a voltage-controlled oscillator for Digital European Cordless Telephone (DECT) applications and a 5-GHz WLAN front end. These examples indicate that this approach yields a compact low-power implementation of complete transceivers for high-performance wireless applications.

The realization of new MPEG-4 functionality, applicable to 3D graphics texture compression and image database access over the Internet, is demonstrated in a PC-based compression system.Applying our system-level design methodologies effectively removes all implementation bottlenecks.A first-of-a-kind ASIC, called Ozone, accelerates the Embedded Zero Tree based encoding and is capable of compressing 30 color CIF images per second.

Standard interfaces for hardware reuse are currently defined at the structural level.In contrast to this, our contribution defines the reuse interface at the behavioral registertransfer (RT) level.This promotes direct reuse of functionality and avoids the integration problems of structural reuse.We present an object oriented reuse interface in C++ and show the use of it within two real-life designs.

No abstract available.

Complex signal processing algorithms are specified in floating point precision. When their hardware implementation requires fixed point precision, type refinement is needed. The paper presents a methodology and design environment for this quantization process. The method uses independent strategies for fixing MSB and LSB weights of fixed point signals. It enables short design cycles by combining the strengths of both analytical and simulation based methods.

Although a single-chip solution seems to be ultimate goal for the design of wireless transceivers, there are many reasons to believe that this approach is not feasible for high performance applications. Especially the RF front-ends of these transceivers require components that are difficult to combine into one single chip. As an alternative we propose a single-package solution that contains different components that are interconnected with a multi-chip module (MCM) interconnect technology. By implementing passive front-end components directly into this interconnect technology, instead of using external commercial components, a cost-effective realization of the front-end can be obtained with a higher performance or a lower power consumption.

The wavelet transform is a popular filter-based decomposition algorithm used in novel multimedia standards and applications. Due to its intrinsic use of filtering operations, the choice of an appropriate filter and the normalisation of its coefficients determines the number of bits needed to represent the transformed image. We show that depending on the normalisation of the filters, the wavelet coefficients either saturate or grow exponentially for successive transformation levels. A procedure to create images that excite worst case maxima in the transform domain is described. The bit-range expansion for natural images is computed and follows the trend of the worst case results.

This paper addresses the problem of minimizing memory size and memory accesses in multiresolution texture coding architectures for discrete cosine transform (DCT) and wavelet-based schemes used, for example, in virtual-world walk-throughs or facial animation scenes of an MPEG-4 system. The problem of minimizing the memory cost is important since memory accesses, memory bandwidth limitations, and in general the correct handling of the data flows have become the true critical issues in designing high-speed and low-power video-processing architectures and in efficiently using multimedia processors. For instance, the straightforward implementation of a multiresolution texture codec typically needs an extra memory buffer of the same size as the image to be encoded/decoded. We propose a new calculation schedule that reduces this buffer memory size with up to two orders of magnitude, while still ensuring a number of external (off-chip) memory accesses that is very close to the theoretical minimum. The analysis is generic and is therefore useful for both wavelet and multiresolution DCT codecs.

A C++ based programming environment for the design of complex high speed ASICs is presented. The design of a 75 Kgate DECT transceiv er is used as a driv er example. Compact descriptions, combined with efficient sim ulationand syn thesis strategies are essen tial for the design of such a complex system. It is sho wn how a C++ programming approach outperforms traditional HDL-based methods.

We reflect on the nature of digital telecommunication systems. We argue that these systems require, by nature, a heterogeneous specification and an implementation with heterogeneous architectural styles. CoWare is a hardware/software co-design environment based on a data model that allows to specify, simulate, and synthesize heterogeneous hardware/software architectures from a heterogeneous specification. CoWare is based on the principle of encapsulation of existing hardware and software compilers and special attention is paid to the interactive synthesis of hardware/software and hardware/hardware interfaces. The principles of CoWare are illustrated by the design process of a spread-spectrum receiver for a pager system.

To construct complete systems on silicon, application specific DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology is presented to synthesize high throughput DSP functions into accelerator processors containing a datapath of highly pipelined, bit-parallel hardware units. Emphasis is put on the definition of a controller architecture that allows efficient run-time schedules of these DSP algorithms on such highly pipelined data paths. The methodology is illustrated by means of an image encoding filter bank.

This paper presents the design of a Videophone Coder-Decoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (complex communication protocol) with a Data Flow Dominated part (high throughput computations) makes this circuit difficult to be synthesized by a single HLS tool. The combination of two HLS tools for the high-level design of this operator required the definition of a sophisticated design flow allowing mixed-level and multi-language simulations. When compared to design starting from RTL specifications, HLS induces only a negligible area overhead of 5%, and provides gain in description length (divided by 5), design time and flexibility.

A just-in-time (JIT) scheduling approach that incorporates register optimizations during scheduling is introduced. The technique is implemented in a hierarchical list scheduler, SMART, that is part of the Cathedral silicon compiler. Due to its computational complexity it can schedule hierarchical graphs containing a thousand or more operations. Experiments on relevant industrial examples show a gain in registers of more than 25% due to the proposed register optimization.>

The authors demonstrate that, next to allocation and scheduling of data path operations, efficient storage schemes and memory access are crucial in DSP (digital signal processor) ASIC (application-specific integrated circuit) design. For complex, medium throughput DSP applications, the authors have identified a strategy and important optimization tasks for compiling multidimensional data structures into distributed dual-port register files and single-port SRAM (static random-access memories). These techniques have been implemented in the Cathedral-II silicon compiler. The applicability of the proposed strategy has been demonstrated during the design of an 800 bit/s vocoder. Window computation reduced 23833 entries of 56 arrays to 932 locations.>

Novel rules to derive the signal flow in a VLSI-design are presented. This method is based on design-style independent logical principles, which makes it suitable for circuits that have not been checked on their electrical correctness. The use of two global principles has an important influence for more complicated designs, but also results in an efficiency penalty which may be kept reasonable by introducing graph reduction rules and heuristics. The different steps in the tagging process are explained and illustrated with examples. The dataflow rules are integrated in the overall DIALOG system to perform electrical verification, and they offer an invaluable help to break up the verification problem in subproblems and to cope with feedback in designs, by introducing the concept of intended unilateral blocks.>

This paper discusses the kernel implementation issues of a new and more formal approach to electrical verification. Rule based analysis of the transistor network is applied to derive the signal flow direction and to identify control and state nodes. Symbolic analysis of Boolean expressions, capturing all aspects of switch level networks, allows to take into account the logical structure of the network and its environment during verification and guarantees more relevant error reports. The application of the proposed strategy on real life examples, demonstrates its usefulness and allows for a realistic evaluation of the tool.

An expert system (DIALOG) is described to check correctness of logic levels and timing composition rules in n- or CMOS VLSI logic. Knowledge is described in an engineer oriented language (LEXTOC) allowing for unification (cfr PROLOG), object creation, property assignment, association of relations, rule formulation, logic or arithmetic evaluation as well as conversational constructs. The system is illustrated by checking racefree dynamic CMOS design composition rules. Up to 250 transistors can be handled in the LISP interpretative way on the VAX 11/780. An efficient automatic translation of LEXTOC into Pascal shows the feasibility for batch oriented debugging of up to 50,000 transistors in a workstation environment, while keeping knowledge programming efficiency of LEXTOC.