As the feature size shrinks, electromigration (EM) becomes a more critical reliability issue in IC design. EM around the via structures accounts for much of the reliability problems in ICs, and the insertion of redundant vias can mitigate the adverse effect of EM by reducing current density. In this paper, we model EM reliability of redundant via structures, considering current distribution with different via layouts. Based on our EM model, we choose redundant via layouts that can increase the EM-related lifetime by using integer linear programming (ILP). To overcome the runtime issue of ILP, we also propose speed-up techniques for our EM-aware redundant via insertion. Experimental results show that our scheme brings much more EM-robustness to circuits with the similar number of redundant vias, compared to the conventional redundant via insertion techniques.

Electromigration (EM) in power distribution networks (PDNs) is a major reliability issue in 3-D ICs. While the EM issues of local vias and through-silicon-vias (TSV) have been studied separately, the interplay of TSVs and conventional local vias in 3-D ICs has not been well investigated. This co-design is necessary when the die-to-die vertical power delivery is done using both TSVs and local interconnects. In this paper, we model EM for PDNs of 3-D ICs with a focus on multiscale via (MSV) structure, i.e., TSVs and local vias used together for vertical power delivery. We study the impact of structure, material, and preexisting void conditions on the EM-related lifetime of our MSV structures. We also investigate the transient IR-voltage change of full-chip level 3-D PDNs with MSVs with our model. The experimental results demonstrate that our EM modeling can effectively capture the EM reliability of the full-chip level 3-D PDNs with MSVs, which can be hard to achieve by the traditional EM analysis based on the individual local via or the TSV.

Electromigration (EM) in power distribution network (PDN) is a major reliability issue in 3D ICs. While the EM issues of local vias and through-silicon-vias (TSV) have been studied separately, the interplay of TSVs and conventional local vias in 3D ICs has not been well investigated. This co-design is necessary when the die-to-die vertical power delivery is done using both TSVs and local interconnects. In this work, we model EM for PDN of 3D ICs with a focus on multi-scale via structure, i.e., TSVs and local vias used together for vertical power delivery. We study the impact of structure, material, and pre-existing void conditions on EM-related lifetime of our multi-scale via structures. Experimental results demonstrate that our EM modeling can effectively capture the EM reliability of the entire multi-scale via in 3D PDN, which can be hard to achieve by the traditional EM analysis based on the individual local via or TSV.

The 3D IC integration using through-silicon-vias (TSV) has gained tremendous momentum recently for industry adoption. However, as TSV involves disruptive manufacturing technologies, new modeling and design techniques need to be developed for 3D IC manufacturability and reliability. In particular, TSVs in 3D IC may cause significant thermal mechanical stress, which not only results in systematic mobility/performance variations, but also leads to mechanical reliability concerns such as interfacial cracking. Meanwhile, the huge dimensional gaps between TSV, on-chip wires, and bonding/packaging all lead to new electromigration concerns. Thus full-chip/package modeling and physical design tools need to be developed to achieve more reliable 3D IC integration. In this paper, we will discuss some key design for manufacturability and reliability challenges and possible solutions for TSV-based 3D IC integration, as well as future research directions.

Electromigration (EM) has become a key reliability concern for nanometer IC designs. For 3D ICs, higher current density/temperature and TSV-induced thermal mechanical stress further exacerbate the EM issue compared to 2D ICs. In this paper, we analyze the root causes of EM for 3D IC signal nets, with consideration of current density, temperature, and TSV-induced thermal mechanical stress. We develop compact EM models for both DC and AC signal nets using detailed finite-element-analysis (FEA) and build EM library for meantime-to-failure (MTTF). For AC signal nets, we convert AC current into equivalent DC current and model EM with it. One unique property of EM in 3D ICs is that, depending on the current direction, TSV-induced stress may degrade or improve the MTTF, thus routing plays an important role for EM mitigation. We suggest EM-aware routing algorithms for 3D ICs for the first time to our best knowledge, guided by our stress-aware EM modeling. Experimental result shows that our proposed approach improves EM-robustness of 3D IC benchmarks significantly, e.g., 66.4% less EM-violated grids with little sacrifice of conventional routing objectives.

3D integration has new manufacturing and design challenges such as timing corner mismatch between tiers and device variation due to Through Silicon Via (TSV) induced stress. Timing corner mismatch between tiers is caused because each tier is manufactured in independent process. Therefore, inter-die variation should be considered to analyze and optimize for paths spreading over several tiers. TSV induced stress is another challenge in 3D Clock Tree Synthesis (CTS). Mobility variation of a clock buffer due to stress from TSV can cause unexpected skew which degrades overall chip performance. In this paper, we propose clock tree design methodology with the following objectives: (a) to minimize clock period variation by assigning optimal z-location of clock buffers with an Integer Linear Program (ILP) formulation, (b) to prevent unwanted skew induced by the stress. In the results, we show that our clock buffer tier assignment reduces clock period variation up to 34.2%, and the most of stress-induced skew can be removed by our stress-aware CTS. Overall, we show that performance gain can be up to 5.7% with our robust 3D CTS.

Electromigration (EM) is a critical problem for interconnect reliability of modern integrated circuits (ICs), especially as the feature size becomes smaller. In three-dimensional (3D) IC technology, the EM problem becomes more severe due to drastic dimension mismatches between metal wires, through silicon vias (TSVs), and landing pads. Meanwhile, the thermo-mechanical stress due to the TSV can also cause reduction in the failure time of wires. However, there is very little study on EM issues that consider TSVs in 3D ICs. In this paper, we show the impact of TSV stress on EM failure time of metal wires in 3D ICs. We model the impact of TSV on stress variation in wires. We then perform detailed modeling of the impact of stress on EM failure time of metal wires. Based on our analysis, we build a detailed library to predict the failure time of a given wire based on current density, temperature and stress. We then propose a method to perform fast full-chip simulation, to determine the various EM related hot-spots in the design. We also propose a simple routing-blockage scheme to reduce the EM related failures near the TSVs, and see its impact on various metrics.