Trajectory prediction is crucial for autonomous vehicles. The planning system not only needs to know the current state of the surrounding objects but also their possible states in the future. As for vehicles, their trajectories are significantly influenced by the lane geometry and how to effectively use the lane information is of active interest. Most of the existing works use rasterized maps to explore road information, which does not distinguish different lanes. In this paper, we propose a novel instance-aware representation for lane representation. By integrating the lane features and trajectory features, a goal-oriented lane attention module is proposed to predict the future locations of the vehicle. We show that the proposed lane representation together with the lane attention module can be integrated into the widely used encoder-decoder framework to generate diverse predictions. Most importantly, each generated trajectory is associated with a probability to handle the uncertainty. Our method does not suffer from collapsing to one behavior modal and can cover diverse possibilities. Extensive experiments and ablation studies on the benchmark datasets corroborate the effectiveness of our proposed method. Notably, our proposed method ranks third place in the Argoverse motion forecasting competition at NeurIPS 20191.

An effective method for mitigating transmitter nonlinear echo in 10GBASE-T transceivers is discussed. This method is based on approximating the nonlinear characteristics of the combined transmitter and the echo channel by smooth multidimensional functions. Results based on a chip fabricated in 0.13 mum CMOS technology show that approximately 6 dB of average cancellation of nonlinear echo can be achieved by this method.

This paper studies the invariance of a given punctured convolutional code to an affine class of symbol transformations known to commonly occur in digital transceiver systems. A set of conditions to test the invariance of a code to these transformations has been derived, followed by two proposed methods to compensate for an invariant transformation. The viability of these methods has been examined by doing an invariant factor decomposition on the equivalent code generator matrix (obtained from the original code generator matrix and the given transform). The knowledge of the transformation and the nature of its occurrence greatly determines which method of compensation could be used. This study has much use in not only enabling a code designer to evaluate the invariance of an affine transformation to a given code, but also on the other hand to make the appropriate choice of code generators, puncturing schemes, and bit-to-constellation symbol mapping; so as to allow a channel coding scheme to be either sensitive or invariant to a given transformation, depending upon design objectives.

A new surviving paths unit (SPU) is described wherein the decision bits produced in the add-compare-select unit (ACSU) of a parallel architecture for the Viterbi algorithm are prepared for efficient storage in a single compact random access memory (RAM). A significant reduction in the size of the RAM is achieved by pre-processing the data in an especially designed unit. The new SPU never requires a memory bandwidth more than the least possible bandwidth imposed by the throughput of the ACSU. A novel interface unit, hereafter referred to as the ACS interface unit (ACSIU), resolves surviving paths down to a pre-determined depth on the trellis diagram of a finite state Markov chain, and breaks the decision bits into a sequence of successive vectors, each of the same size as the word-size of the RAM. At any trace-back step, a subset of the previous content of the trace-back register is used to generate the address for the current output of the RAM. A disjoint subset of the current content of the trace-back register is used to select a pre-determined number of bits from the output of the RAM. The selected bits are used to update the content of the trace-back register. The trace-back register after a sufficient number of trace-back steps, contains the estimated bits.

The problem of decoding cyclic error correcting codes is one of solving a constrained polynomial congruence, often achieved