The rapid adoption of the open and extensible RISC-V instruction set architecture across diverse computing domains requires a thorough understanding of its security posture, particularly against hardware threats. While performance optimizations like speculative and out-of-order execution enhance throughput, they concurrently introduce vulnerabilities to Transient Execution Attacks (TEAs), which can bypass traditional security mechanisms. The inherent flexibility of RISC-V leads to significant microarchitectural variation among implementations, suggesting that susceptibility to TEAs is not uniform. However, systematic comparative assessments across prominent processors are still lacking. This paper addresses this gap by presenting a comparative vulnerability analysis of three widely used open-source RISC-V cores: the high performance BOOM, the reliability-oriented NOEL-V, and CVA6. We ported and evaluated a set of TEAs, including variants of Spectre and Meltdown and the most recent attacks, such as Speculative Code Store Bypass (SCSB) and Indirector. Our experiments demonstrate the successful execution of different attack subsets on each processor, revealing distinct vulnerability profiles tied to their underlying microarchitectures, offering valuable vulnerability data and practical insights that may be crucial for guiding the design of more secure processors. One of the key insights of our analysis is that, contrary to the popular belief, in-order processors are vulnerable against TEAs.

RISC-V is increasingly considered a strategic architecture for technological sovereignty and long-term platform independence, yet its practical maturity across software, performance and security is still debated. This paper presents an integrated, hardware-grounded assessment of the current RISC-V ecosystem. We first analyze software readiness by examining toolchain fragmentation, operating-system integration, and deployment effort across commercial ASIC boards and configurable FPGA soft-cores. We then benchmark representative processors using CoreMark, Geekbench 6, and SPEC2017, and contextualize the achieved results through direct comparison with contemporary ARM and x86 systems. Finally, we evaluate susceptibility to Transient Execution Attacks on three prominent open-source cores (BOOM, NOEL-V, and CVA6). The results show a clear three-way trade-off. Software support remains heterogeneous: ASIC platforms provide faster bring-up, whereas soft-core deployments require substantial hardware-software codesign effort. From a performance perspective, the best evaluated RISC-V ASIC demonstrates competitive per-cycle efficiency for embedded-class workloads, but a significant gap persists versus high-end proprietary processors; on FPGA soft-cores, low frequency and memory-system constraints often prevent completion of demanding benchmark suites. From a security perspective, all evaluated open-source cores are vulnerable to a subset of transient-execution attacks, with broader attack surfaces associated with more aggressive speculative microarchitectures. Overall, RISC-V is already a deployable opportunity for customizable embedded domains. For high-performance, general-purpose use, closing the gap requires coordinated ecosystem consolidation and rigorous security-by-design co-validation across hardware and software layers.

The open and modular nature of the RISC-V Instruction Set Architecture (ISA) has produced a fragmented landscape of hardware implementations and software environments, with direct consequences on portability, performance, and resilience to hardware attacks. The practical maturity of its most prominent cores, however, is rarely assessed in a unified manner and on real hardware rather than in simulation. This paper presents such an evaluation for six representative cores: three commercial ASICs (SiFive P550, Orange Pi RV2, Microchip PIC64GX) and three configurable FPGA-based soft-cores (BOOM, NOEL-V, CVA6). We study them along three complementary axes, namely the maturity of their software environments, distilled from hands-on deployment; their computational performance, measured with CoreMark, Geekbench 6, and SPEC2017 and contextualised against ARM and x86 cores; and the susceptibility of the open-source soft-cores to a comprehensive set of Transient Execution Attacks (TEAs). Our results identify the SiFive P550 as the strongest performer, comparable with mid-range embedded ARM cores but well behind high-end ARM and x86 designs; they show that the tested soft-core deployments are not yet ready for complex general-purpose workloads; and they reveal that even in-order cores are vulnerable to TEAs, with distinct profiles tied to their microarchitectures.

Transient Execution Attacks (TEAs) exploit architectural optimizations in modern processors, such as out-of-order and speculative execution, to illicitly access sensitive data belonging to other processes or the operating system. While the RISC-V ISA has gained significant traction, its susceptibility to TEAs remains relatively unexplored. A major obstacle to in-depth security evaluation of RISC-V processors is the lack of readily accessible and comprehensive TEA implementations for these architectures. This paper introduces Security for RISC-V (S4V), a security benchmark suite comprising implementations of several recent TEAs specifically tailored for RISC-V processors. Beyond providing a template for each TEA implementation, we developed an instance of S4V for the Berkeley Out-of-Order Machine (BOOM) processor to demonstrate the feasibility of executing these attacks on a widely adopted and renowned RISCV core. S4V aims to facilitate security research in evaluating countermeasures and enabling a more thorough understanding of TEA vulnerabilities within the RISC-V ecosystem.

The quest of low production cost and short time-to-market, as well as the complexity of modern integrated circuits pushed towards a globalization of the supply chain of silicon devices. Such production paradigm raised a number of security threats among which Hardware Trojan Horses (HTHs), that became a serious issue not only for academy but also for industry in the very last years. Indeed, it has been demonstrated that HTHs can be inserted into microprocessors allowing the attacker to run malicious software, to acquire root privileges or to steal secret information. In this paper we present the use of software obfuscation to protect systems against HTHs that aim at stealing information from the microprocessor while it is executing a program. Moreover, we present a Genetic Algorithm-based approach to optimize such anti-HTH methodology by maximizing the obtained obfuscation while minimizing the introduced overhead. We proved the effectiveness and efficiency of the proposed methodology on the Ariane 64bit RISC-V microprocessor running a set of MiBench benchmarks and cryptographic programs.