This paper presents a low input-referred-noise (IRN) discrete-time (DT) delta-sigma modulator (DSM) for precise biopotential-signal acquisition. The proposed structure utilizes a 1st-order input-impedance-boosted kT/C-noise-cancellation integrator combined with a 2nd-order noise-shaping SAR (NS-SAR). The proposed integrator cancels the kT/C noise generated during the sampling and integrating phases by using feedback capacitors for the cancellation loop while boosting the input impedance. This novel integrator can utilize smaller capacitors for sampling and integration than the standard design without any performance degradation. A single amplifier in the integrator is reused for sampling, kT/C noise cancellation, and integration to reduce power consumption. The NS-SAR is utilized instead of an amplifier-based multistage integrator structure to attain high resolution while maintaining low power consumption. The prototype IC, simulated using a 65-nm CMOS process, achieves a 90.5-dB SNDR across a 1-Hz-to-1-kHz bandwidth with a 300-mVPPinput, yielding a 99.8-nV/$\sqrt {{\text{Hz}}} $ IRN and a FoMSNDRof 173.4 dB. These results indicate that the proposed DSM can properly acquire biopotential signals from both muscular and cardiac sources.

A hybrid high-voltage regulating charge pump is proposed for point-of-care electrokinetic concentration chip applications. The hybrid charge pump is composed of three cascaded sub-pumps. High efficiency, minimized area, wide output current range, and high regulated output voltage are achieved by selecting charge pump architectures that provide high voltage conversion gain with less number of stages. The proposed charge pump is designed and fabricated in 180 nm BCD process. Simulation results show that the proposed system provides a maximum efficiency of 48.26%, while providing a maximum output voltage of 65 V.

The measurement of small variation of the bioZ having a substantially large baseline impedance is a great challenge, requiring a wide dynamic range (DR) and a high signal-to-noise ratio (SNR). This paper presents a new impedance measurement architecture based on Δ-ΔΣ modulator with capacitive-feedback baseline cancellation. The readout front-end (RFE) of the integrated circuit (IC) is configured with a first-order Δ-ΔΣ modulator and a feedback capacitive digital-to-analog converter (CDAC) that minimize the power consumption. The front-stage Δ-modulation allows to achieve a wide input DR of 30 kΩ by eliminating the large static baseline impedance with no static current consumption. It also mitigates the input-dependent noise characteristic of the current balancing instrumentation amplifier (CBIA) significantly. The current generator (CG) generates a square wave for the excitation current with a current magnitude ranging from 5 μApkto 100 μApkover a frequency range from 1 kHz to 1024 kHz. The chopping and dynamic element matching (DEM) techniques are adopted in the bandgap reference (BGR), CG, and current-DAC (IDAC) to mitigate their flicker noises, which dominate the signal bandwidth (<10 Hz). The proposed IC designed in a 180-nm CMOS process consumes only 7.64 μW for the I path of the RFE, achieving a maximum SNR of 97.7 dB.

In analog-mixed-signal (AMS) compute-in-memory (CIM) systems, the two’s-complement (2SC) format provides better area efficiency than the sign-and-magnitude (SNM) one. However, the 2SC format exacerbates the challenges of AMS-CIM systems, suffering from significant DNN accuracy drop under process variations and high computation currents from activating multiple WLs. In the 2SC format, ‘0’ and ‘1’ are nearly balanced for all logical-order bits, unlike ‘0’-skewed higher-order bits in the SNM format. Consequently, the 2SC-based AMS-CIM systems have much more on-cells than the SNM-based counterpart, deteriorating the above challenges. We propose Skew-CIM, a software-hardware co-design technique to relax these challenges. Our proposed weight skewing (WESK) breaks the ‘0’ and ‘1’ balance at the software level. The potential accuracy drops resulting from WESK are successfully compensated by retraining DNNs. The offsets caused by WESK can be easily corrected using online hardware-level processing. Our Skew-CIM technique can be applied to most AMS-CIM systems with memories showing large on-off cell current ratios. As an example, we use it in a custom-designed 8T-SRAM-based CIM device, demonstrating a significant reduction in the DNN classification error by 7.6 times compared to the 2SC-based AMS-CIM without our Skew-CIM technique. Furthermore, our Skew-CIM markedly enhances energy efficiency by up to 39.9%, outperforming conventional SNM-based AMS-CIM systems.