Zhuokai Zhou

dblp:320/9863 · DBLP profile ↗
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3ranked-venue papers
0as first author
3since 2021 · last 2022
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Storage systems · 73% Memory systems · 12% Cloud and datacenter computing · 12%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems
flash and SSD
1.122022
MAID-Q: Minimizing Tail Latency in Embedded Flash With SMR Disk via -Learning Model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
Rebirth-FTL: Lifetime Optimization via Approximate Storage for NAND Flash Memory · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
Storage systems
storage reliability
0.722022
Rebirth-FTL: Lifetime Optimization via Approximate Storage for NAND Flash Memory · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
MAID-Q: Minimizing Tail Latency in Embedded Flash With SMR Disk via -Learning Model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
Storage systems › energy-efficient storage
approximate storage
0.612022
Rebirth-FTL: Lifetime Optimization via Approximate Storage for NAND Flash Memory · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
Memory systems › non-volatile memory
embedded flash memory
0.612022
MAID-Q: Minimizing Tail Latency in Embedded Flash With SMR Disk via -Learning Model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
Storage systems › flash and SSD › flash memory management
flash translation layer
0.612022
Rebirth-FTL: Lifetime Optimization via Approximate Storage for NAND Flash Memory · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
Storage systems › magnetic recording
shingled magnetic recording
0.612022
MAID-Q: Minimizing Tail Latency in Embedded Flash With SMR Disk via -Learning Model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
Cloud and datacenter computing › quality of service
tail latency
0.612022
MAID-Q: Minimizing Tail Latency in Embedded Flash With SMR Disk via -Learning Model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
Embedded and real-time systems › real-time scheduling
resource reclaiming
0.212022
MAID-Q: Minimizing Tail Latency in Embedded Flash With SMR Disk via -Learning Model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022

Methods — techniques the papers use, named apart from their topics

wear leveling · 0.6reinforcement learning · 0.6q-learning · 0.6garbage collection · 0.6address translation · 0.6
YearPublicationVenuePosition
2022 MU-RMW: Minimizing Unnecessary RMW Operations in the Embedded Flash with SMR Disk
abstract
Emerging Shingled Magnetic Recording (SMR) Disk can improve the storage capacity significantly by overlapping multiple tracks with the shingled direction. However, the shingled-like structure leads to severe write amplification caused by RMW operations inner SMR disks. As the mainstream solid-state storage technology, NAND flash has the advantages of tiny size, cost-effective, high performance, making it suitable and promising to be incorporated into SMR disks to boost the system performance. In this hybrid embedded storage system (i.e., the Embedded Flash with SMR disk (EF-SMR) system), we observe that physical flash blocks can contain a mixture of data associated with different SMR data bands; when garbage collecting such flash blocks, multiple RMW operations are triggered to rewrite the involved SMR bands and the performance is further exacerbated. Therefore, in this paper, we for the first time present MU-RMW to guarantee data from different SMR bands will not be mixed up within the flash blocks with an aim at minimizing unnecessary RMW operations. The effectiveness of MU-RMW was evaluated with realistic and intensive I/O workloads and the results are encouraging.
Chenlin Ma, Zhuokai Zhou, Yingping Wang, Yi Wang 0003, Rui Mao 0001
DATE2
2022 Rebirth-FTL: Lifetime Optimization via Approximate Storage for NAND Flash Memory
abstract
The lifetime of NAND flash cells significantly degrades with feature-size reductions and multilevel cell technology. On the other hand, we have more and more approximate data, such as images and videos that are more error tolerant than regular data like text. In this article, we propose Rebirth-FTL, which reuses faulty blocks that contain uncorrectable errors to store approximate data for lifetime optimization. Rebirth-FTL effectively manages two spaces, namely, the approximate space and the normal space, with an efficient address translator, a coordinated garbage collection, and a differential wear leveler. In addition, we develop an migration times restriction (MTR) policy to restrict the movement of the approximate data in the approximate space. We also develop a scheme to pass approximate information from userland to kernel space in Linux. Finally, a lifetime model is presented for lifetime analysis. Our experimental results show that Rebirth-FTL can extend the lifetime by 41.63% on average.
Chenlin Ma, Zhuokai Zhou, Zhaoyan Shen, Yi Wang 0003, Renhai Chen, Zili Shao
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2022 MAID-Q: Minimizing Tail Latency in Embedded Flash With SMR Disk via -Learning Model
abstract
As the mainstream solid-state storage technology, NAND flash has the advantages of tiny size, cost-effective, and high performance, which make it a promising candidate to be embedded into the shingled magnetic recording (SMR) disk to build a faster, denser, and cheaper storage system. However, such an embedded flash with SMR (EF-SMR) disk system suffers from lengthy tail-latency due to “reclamation issues” in both the NAND flash and the SMR disk. Our preliminary observations reveal that tremendous idle time intervals exist in real-world scenarios, and few prior works have focused on addressing the tail-latency issue in the EF-SMR disk. In this article, we propose a novel method termed MAID-Q to fully exploit the idle time intervals to minimize the lengthy tail-latency of the EF-SMR disk based on a lightweight reinforcement learning model (i.e., the$Q$-learning model). In addition, fine-grained block-level space management and a parallel reclamation strategy are proposed to improve the reclamation efficiency and hide the reclamation overheads. The effectiveness of our proposed design was evaluated with realistic I/O traces, and the results show that the proposed design can remedy the tail-latency by 88.31% and improve the overall performance by 79.03%.
Chenlin Ma, Zhuokai Zhou, Yingping Wang, Yi Wang 0003, Rui Mao 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2