Spiking Neural Networks (SNNs) have demonstrated remarkable potential across many domains, including computer vision and natural language processing, owing to their energy efficiency and biological plausibility. However, their application in long-term prediction tasks remains underexplored, which is primarily due to two critical challenges: (1) current SNN encoding methods are unable to effectively encode long temporal information, leading to increased computational complexity and energy consumption; (2) though Transformer-based models have achieved state-of-the-art accuracy in temporal prediction tasks, the absence of proper positional encoding for spiking self-attention restricts Spiking Transformer from effectively utilizing positional information, resulting in performance degradation. To address these challenges, we introduce an attention-free framework, **Spik**ing **F**ourier Network (**SpikF**), that encodes input sequences in patches and employs an innovative frequency domain selection mechanism to effectively utilize the sequential properties of time-series data. Extensive evaluations on eight well-established long-term prediction datasets demonstrate that SpikF achieves an averaged $1.9\\%$ reduction in Mean Absolute Error (MAE) compared to state-of-the-art models, while lowering total energy consumption by $3.16\times$. Our code is available at https://github.com/WWJ-creator/SpikF.

Asynchronous circuits become an attractive alternative to synchronous circuits owing to their potential benefits such as low power consumption, and no clock distribution problems. However, handshake control and relative timing analysis make designing asynchronous circuits a complex and error-prone task. Moreover, traditional electronic design automation (EDA) tools are tailored specifically for synchronous circuits, resulting in significant manual effort when designing asynchronous circuits. To address these issues, this paper proposes a desynchronization method based on Chisel, which converts synchronous circuits into bundled-data asynchronous ones automatically. For demonstration, an open-source synchronous RISC-V processor is desynchronized to an asynchronous one, and both are implemented on Zynq7020 FPGA. The experimental results illustrate that the power consumption of Clicks for handshaking in the desynchronized processor is only 33.3% of that of the global clocks in the synchronous one. Besides, with Clicks the power consumption of memory access is reduced by 80%. Compared with previous synchronous and asynchronous RISC-V processors, the asynchronous RISC-V processor achieves up to 8.4x and 1.5x dynamic power reductions respectively.

Event-driven asynchronous neuromorphic hardware is emerging for edge computing with high energy efficiency. In order to obtain the architecture with the best hardware performance, we need to search both the numerical and non-numerical design space of asynchronous neuromorphic hardware. However, it is challenging to find an optimal hardware architecture from the non-numerical design space. To address this problem, we propose an asynchronous neuromorphic hardware architecture search (ANAS) method, which uses an evolutionary algorithm to optimize both the numerical and non-numerical design space. Besides, we introduce a configurable asynchronous neuromorphic hardware simulator (CanMore) to offer system-level modeling and performance estimation. Experimental results show that ANAS rivals the best human-designed architecture by 7 × EDP reduction, and offers 2.3 × EDP reduction than the methods that only optimize numerical design space.