Minhyuk Kweon

dblp:321/5622 · DBLP profile ↗
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4ranked-venue papers
0as first author
4since 2021 · last 2026
0000-0002-1539-8491ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
YearPublicationVenuePosition
2026 Timing- and Power-Aware Differentiable Repair of Minimum Implant Area Violations
Jinoh Cho, Minhyuk Kweon, Jinmo Ahn, Jeyeong Park, Seokhyeong Kang
ISLPED2
2024 Improvement of Mixed Track - Height Standard-Cell Placement
abstract
In sub-Snm nodes, track-height of standard cells must be aggressively scaled down while preserving design PPA. This requirement brings the challenge of placing a set of cells that have mixed track-heights, subject to the constraint that cells with the same height must be placed together in an “island” of cell rows. We apply integer linear programming (ILP) to solve the row assignment problem and improve the runtime of ILP with clustering, using a cost function that combines half-perimeter wirelength and displacement from a starting unconstrained placement. Considering the row assignment solution, we define fence-regions, which enable an existing place-and-route (P&R) tool to place the cells while considering the row-island constraints. Experimental results show that our proposed method can on average reduce final-routed wirelength by 8.5% and total power by 3.3 %, with worst negative slack and total negative slack reductions of 24.0% and 13.0%, compared with the previous state-of-the-art method [10].
Andrew B. Kahng, Seokhyeong Kang, Minhyuk Kweon
DATE3
2022 A fast and scalable qubit-mapping method for noisy intermediate-scale quantum computers
abstract
This paper presents an efficient qubit-mapping method that redesigns a quantum circuit to overcome the limitations of qubit connectivity. We propose a recursive graph-isomorphism search to generate the scalable initial mapping. In the main mapping, we use an adaptive look-ahead window search to resolve the connectivity constraint within a short runtime. Compared with the state-of-the-art method [15], our proposed method reduced the number of additional gates by 23% on average and the runtime by 68% for the three largest benchmark circuits. Furthermore, our method improved circuit stability by reducing the circuit depth and thus can be a step forward towards fault tolerance.
Sunghye Park, Minhyuk Kweon, Jae-Yoon Sim, Seokhyeong Kang
DAC3
2022 GAN-Dummy Fill: Timing-aware Dummy Fill Method using GAN
abstract
The chemical mechanical polishing (CMP) dummy fill method is commonly used for the planarization of the CMP process, resulting in the development of many automated methods. We propose a dummy fill method using a generative adversarial network (GAN) that improves the existing dummy fill methods in terms of the uniformity of metal density and timing of critical nets. The dummy patterns created were similar to those of existing methods. However, the GAN dummy fill method applies additional optimizations to make the CMP dummy fill pattern efficient. The method learns by adding density and parasitic capacitance to the loss function of the GAN. Compared to dummy patterns generated from commercial tools, dummy patterns generated from GAN-dummy fill reduced the negative timing slack due to parasitic capacitance by up to 45%.
Myong Kong, Minhyuk Kweon, Seokhyeong Kang
ACM Great Lakes Symposium on VLSI3