The premise of semi-supervised learning (SSL) is that combining labeled and unlabeled data yields significantly more accurate models. Despite empirical successes, the theoretical understanding of SSL is still far from complete. In this work, we study SSL for high dimensional sparse Gaussian classification. To construct an accurate classifier a key task is feature selection, detecting the few variables that separate the two classes. For this SSL setting, we analyze information theoretic lower bounds for accurate feature selection as well as computational lower bounds, assuming the low-degree likelihood hardness conjecture. Our key contribution is the identification of a regime in the problem parameters (dimension, sparsity, number of labeled and unlabeled samples) where SSL is guaranteed to be advantageous for classification. Specifically, there is a regime where it is possible to construct in polynomial time an accurate SSL classifier. However, any computationally efficient supervised or unsupervised learning schemes, that separately use only the labeled or unlabeled data would fail. Our work highlights the provable benefits of combining labeled and unlabeled data for classification and feature selection in high dimensions. We present simulations that complement our theoretical analysis.

Two important attributes of analog to digital converters (ADCs) are its sampling rate and dynamic range. The sampling rate should be greater than or equal to the Nyquist rate for bandlimited signals with bounded energy. It is also desired that the signals’ dynamic range should be within that of the ADC’s; otherwise, the signal will be clipped. A modulo operator has been recently suggested prior to sampling to restrict the dynamic range. Due to the nonlinearity of the modulo operation, the samples are distorted. Existing recovery algorithms to recover the signal from its modulo samples operate at a high sampling rate and are not robust in the presence of noise. In this paper, we propose a robust algorithm to recover the signal from the modulo samples which operates at lower sampling rate compared to existing techniques. We also show that our method has lower error compared to existing approaches for a given sampling rate, noise level, and dynamic range of the ADC. Our results lead to less constrained hardware design to address dynamic range issues while operating at the lowest rate possible.