Demo Data from EDBT 2026 / reviewers in the wild / expert
Alec N. Broers
dblp:322/6250
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1991
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 67% Integrated circuit design · 33% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design › lithography
electron beam lithography |
0.0 | 1 | 1991 | Limits of nano-gate fabrication · Proc. IEEE 1991 |
Electronic design automation › physical design
lithography |
0.0 | 1 | 1991 | Limits of nano-gate fabrication · Proc. IEEE 1991 |
Methods — techniques the papers use, named apart from their topics
sacrificial layer patterning · 0.0e-beam exposure · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1991 | Limits of nano-gate fabricationabstractThe authors review the limits of nanometer-scale gate electrode (nano-gate) fabrication. The technology to fabricate nano-gates has become increasingly important in recent years as the scaling limits of conventional electronic devices and the quantum effects of novel devices are investigated. Consistent with the technology used to fabricate virtually all of the smallest devices to date, the emphasis is on the resolution limits of electron beam lithography and associated ultrahigh resolution resists. Recent results of directly patterning SiO/sub 2/ with nanometer-scale resolution by e-beam exposure through a sacrificial layer are also presented. Because the high resistance normally associated with nanometer-scale electrodes seriously limits the performance of high-frequency devices, various techniques to reduce the gate resistance are compared.> David R. Allee, Alec N. Broers, R. Fabian W. Pease |
Proc. IEEE | 2 |