EDBT 2026 Demo / reviewers in the wild / expert
Giorgio Farina
dblp:323/5170
· DBLP profile ↗
5ranked-venue papers
3as first author
5since 2021 · last 2026
0009-0002-2612-9884ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021Security and privacy · 3 · 1 first-author · 3 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | AnBridge: Protecting On-Device AI with Android Virtualization Framework
Giorgio Farina, Raffaele Della Corte, Aravind Machiry, Marcello Cinque, Saurabh Bagchi |
DSN | 1 |
| 2025 | COSMOS: A Fault Injection Framework to Assess Hardware-Assisted HypervisorsabstractHardware-assisted virtualization represents a pillar technology for large-scale clusters and cloud-based applications. Hardware faults are still frequent as technology advances, potentially resulting in serious reliability concerns. This paper introduces COSMOS, a fault injection framework tailored for testing hardware-assisted hypervisors. By exploiting nested virtualization, COSMOS does not require instrumentation of the target and enables the assessment of multiple hypervisors. We performed an extensive fault injection campaign to assess popular hardware-assisted hypervisors like KVM, Xen, and Jailhouse. The results show a non-negligible percentage of non–fail-stop behaviors, with notable differences in hypervisors’ ability to log failures and prevent fault propagation with a timely recovery. Marcello Cinque, Domenico Cotroneo, Giuseppe De Rosa, Luigi De Simone, Giorgio Farina |
IEEE Trans. Dependable Secur. Comput. | 5 |
| 2023 | IRIS: a Record and Replay Framework to Enable Hardware-assisted Virtualization FuzzingabstractNowadays, industries are looking into virtualization as an effective means to build safe applications, thanks to the isolation it can provide among virtual machines (VMs) running on the same hardware. In this context, a fundamental issue is understanding to what extent the isolation is guaranteed, despite possible (or induced) problems in the virtualization mechanisms. Uncovering such isolation issues is still an open challenge, especially for hardware-assisted virtualization, since the search space should include all the possible VM states (and the linked hypervisor state), which is prohibitive. In this paper, we propose IRIS, a framework to record (learn) sequences of inputs (i.e., VM seeds) from the real guest execution (e.g., OS boot), replay them as-is to reach valid and complex VM states, and finally use them as valid seed to be mutated for enabling fuzzing solutions for hardware-assisted hypervisors. We demonstrate the accuracy and efficiency of IRIS in automatically reproducing valid VM behaviors, with no need to execute guest workloads. We also provide a proof-of-concept fuzzer, based on the proposed architecture, showing its potential on the Xen hypervisor. Carmine Cesarano 0002, Marcello Cinque, Domenico Cotroneo, Luigi De Simone, Giorgio Farina |
DSN | 5 |
| 2023 | Enabling memory access isolation in real-time cloud systems using Intel's detection/regulation capabilitiesabstractThe increasing interest in adopting cloud technologies for Industry 4.0 and mixed-criticality environments is paving the way for compelling new opportunities and challenges. However, cloud deployments use multicore processors that introduce interference between co-executing applications on different cores due to contention in shared resources, such as the memory subsystem. Such interference can cause critical applications to miss their deadlines. To enable the co-execution of critical and non-critical applications on the same multicore processor, we propose an approach that guarantees memory access time isolation for critical cores, while not jeopardizing the memory bandwidth of the non-critical ones. We prove the viability of our approach using Intel’s resource director technology for memory access detection and regulation. Experiments show that queue occupancy is an excellent metric to estimate the number of interfering cores co-accessing the memory. We also assess the indirect memory bandwidth limitation achievable by applying Intel’s Memory Bandwidth Allocation technology. Giorgio Farina, Gautam Gala, Marcello Cinque, Gerhard Fohler |
J. Syst. Archit. | 1 |
| 2022 | Assessing Intel's Memory Bandwidth Allocation for resource limitation in real-time systemsabstractIndustries are recently considering the adoption of cloud computing for hosting safety critical applications. However, the use of multicore processors usually adopted in the cloud introduces temporal anomalies due to contention for shared resources, such as the memory subsystem. In this paper we explore the potential of Intel’s Memory Bandwidth Allocation (MBA) technology, available on Xeon Scalable processors. By adopting a systematic measurement approach on real hardware, we assess the indirect memory bandwidth limitation achievable by applying MBA delays, showing that only given delay values (namely 70, 80 and 90) are effective in our setting. We also test the derived bandwidth assured to a hypothetical critical core when interfering cores (e.g., generating a concurrent memory access workload) are present on the same machine. Our results can support designers by providing understanding of impact of the shared memory to enable predictable progress of safety critical applications in cloud environments. Giorgio Farina, Gautam Gala, Marcello Cinque, Gerhard Fohler |
ISORC | 1 |