Artificial Intelligence hardware accelerators are pervading the chip market. Most of the time, they are third-party IPs integrated by silicon manufacturers. As a consequence, their design may be obfuscated, which can introduce issues from a manufacturing testing perspective. This paper illustrates how to effectively and efficiently select the most appropriate functional stress stimuli for Artificial Intelligence (AI) Hardware (HW) Accelerators embedded in System-on-Chip (SoC). The proposed methodology is netlist independent; and it is based on both current measurements from the real chip and architectural evaluations. These ingredients are heuristically used to rank and sift the optimal functional patterns to apply along the Burn-In (BI) phase. Experimental results on two different Automotive SoCs manufactured by STMicroelectronics, demonstrate the effectiveness and efficiency of the proposed method.

Traditional structural tests do not provide comprehensive coverage of all possible faults in automotive System-on-Chips (SoCs). To address these gaps, the manufacturing test flow now incorporates System-Level Test (SLT), an additional holistic test phase that executes advanced functional test programs. This research advances SLT methodologies by introducing a stress-optimization approach that targets critical, non-uniformly stressed areas, complementing structural stress methods. It also provides practical guidelines for developing SLT suites that effectively test SoC communication peripherals. Additionally, automated SLT workload generation techniques leverage graph-based SoC abstractions and Device Tree Source (DTS) files to reduce manual effort. Furthermore, grading methodologies are proposed to evaluate SLT effectiveness using high-level metrics derived from instruction traces, enabling early feedback without exhaustive fault simulation. The proposed methods are validated on a 40nm automotive SoC, manufactured by STMicroelectronics, with approximately 20 million logic gates, using a low-cost, FPGA-based modular tester. Experimental results demonstrate that SLT suites can significantly enhance the quality and reliability of automotive SoCs. Collectively, these contributions make SLT more scalable, automated, and effective, meeting stringent automotive quality standards and enabling broader application in domains such as data center processors.

Nowadays, AI applications are becoming extremely popular in our everyday life as well as for the industry. Recent incidents involving hyperscalers have revealed that even cloud-based datacenter hardware can experience failures leading to Silent Data Corruptions (SDCs), also called Silent Data Errors (SDEs). This Special Session delves into the implications of such failures on AI workloads, both during training and inference, and explores methodologies for efficiently detecting SDCs or SDEs through dedicated monitoring phases.

Developing functional test programs for hardware testing is time-consuming and experience-wise. A functional test program’s quality is usually assessed only through expensive fault simulation campaigns during early development. This paper presents indirect quality measurements of fault detection capabilities of functional test programs to reduce the total cost of fault simulation in the early development stages. We present a methodology that analyzes the instruction trace generated by running functional test programs on-chip and building its control and dataflow graph. We use the graph to identify potential flaws that affect the program’s fault detection capabilities. We present different graph-based techniques to measure the programs’ quality indirectly. By exploiting standard debugging formats, we individuate instructions in the source code that affect the graph-based measurements. We perform experiments on an automotive device manufactured by STMicroelectronics, running functional test programs of different natures. Our results show that our metric allows test engineers to develop better functional test programs without basing their development solely on fault simulation campaigns.

This paper deals with functional System-Level Test (SLT) for System-on-Chips (SoCs) communication peripherals. The proposed methodology is based on analyzing the potential weaknesses of applied structural tests such as Scan-based. Then, the paper illustrates how to develop a functional SLT programs software suite to address such issues. In case the communication peripheral provides detection/correction features, the methodology proposes the design of a hardware companion module to be added to the Automatic Test Equipment (ATE) to interact with the SoC communication module by purposely corrupting data frames. Experimental results are obtained on an industrial, automotive SoC produced by STMicroelectronics focusing on the Controller Area Network (CAN) communication peripheral and showing the effectiveness of the SLT suite to complement structural tests.

Traditional structural tests are powerful automatic approaches for capturing faulty behavior in integrated circuits. Besides the ease of generating test patterns, structural methods are known to be able to cover a vast but incomplete spectrum of all possible faults in a System-on-Chip (SoC). A new step in the manufacturing test flow has been added to fill the leftover gaps of structural tests, called the System-Level Test (SLT), which resembles the final workload, and environment.This work illustrates how to build up an automated generation engine to synthesize SLT programs that effectively attack structural test weaknesses from both a holistic and an analytical perspective. The methodology targets the crossbar module, as one of the most critical areas in the SoC, and it simultaneously creates a ripple effect across the un-core logic.Experimental results are conducted on an automotive SoC manufactured by STMicroelectronics.

The rising complexity of integrated devices has led to new defect types and failure modes at the system level that are not detected by structural tests. System-Level Test (SLT) is another test step to combat this challenge. SLT is in charge of exercising system-level interactions between hardware components and software. Non-functional properties, e.g., temperature, play a major role in SLT.This work focuses on the automatic generation of assembly test programs for SLT that aim to indirectly maximize a particular non-functional property, for example, the temperature. It is based on two-step generation with genetic algorithms. First, a fast architectural simulation is used with the genetic algorithm to provide a structure for the test programs. Afterward, an additional generation is done on the hardware to optimize the initial register contents of the program.The case study for gathering experimental results is a super-scalar out-of-order RISC-V processor, the Berkeley Out-of-Order Machine (BOOM). Experimental results show that the two-step generation is more effective in converging to a better power-hungry test program than only using the power consumption as a fitness function for the genetic algorithm.

Functional test programs are increasingly used as flexible approaches to verify device functionality, both online (e.g., Software-Based Self Tests encapsulated in Software Test Library) and during the manufacturing test flow (e.g., System-Level Test). However, a traditional integrated development environment seldom analyzes functional test program weaknesses regarding fault-masking and propagation in CPU registers. Therefore, understanding the presence of errors in the programs due to logic faults at the end of the test program is only assessed by a signature computation, e.g., xor operation between all registers. The presence of program weaknesses in terms of data or control flow is not assessed, and it may lead to fault escapes and/or masking. In particular, those are perfect conditions for proliferating Silent data corruption and unrecoverable errors at the system level.This work aims to introduce a guided debugger-based fault injector framework to verify the fault propagation and masking capabilities of functional test programs by eventually catching program errors without relying on time-consuming simulation-based approaches. The fault-free instruction trace is dumped and analyzed to provide information about possible target registers of specific instructions for injecting faults, e.g., in jump instructions, where errors into registers may change the execution flow or not, to verify the presence of silent data corruptions and errors.The experimental results are carried out on an automotive device from the SPC58 family manufactured by STMicroelectronics, and faults are injected through a script running on Power Debug E40 from Lauterbach.

Burn-In test equipment usually owns extensive memory capabilities to store pre-computed patterns to be applied to the circuit inputs as well as ad-hoc circuitries to drive and read the DUT pins during the BI phase. The solution proposed in this paper dramatically reduces the memory size requirement and just demands a generic microcontroller unit (MCU) equipped with a couple of embedded processors, some standard common peripheral units, and a few KB memories. Moreover, the proposed Burn-In tester could be integrated into a System Level Test equipment which is typically based on MCUs to communicate functionally with the DUT. This paper provides full details about the architecture of such a low-cost innovative tester, which can supply the DUT with unlimited pseudo-random patterns created autonomously by the MCU firmware from any selected seed. The tester prototype developed to collect experimental results includes a low-cost System-on-Chip based on a multi-core MCU and a set of peripheral cores, encompassing timers and Direct Memory Access modules. The tester prototype is used to stress an automotive chip accounting for about 20 million gates, 700 thousand scan flip-flops, and several scan modes. The combination of pseudo-random pattern generation with the ability to control different scan and Design for Testability (DfT) modes, including LBIST, permits to reach a higher coverage of stress metrics than by the application of a limited set of pre-computed ATPG patterns. The toggle coverage level reached is up to 95.89%. The application speed achieved by the tester with non-optimized connections is up to about 10MHz.

This paper encompasses three contributions by industry professionals and university researchers. The contributions describe different trends in automotive products, including both manufacturing test and run-time reliability strategies. The subjects considered in this session deal with critical factors, from optimizing the final test before shipment to market to in-field reliability during operative life.

The complexity of automotive Systems-on-a-Chip (SoCs) has enormously grown in the last decades. Today’s automotive SoCs are compelling due to technology improvements, different integration technologies, increased heterogeneity, and many available embedded memories. On balance, despite testing techniques that have been refined through years, traditional structural test methods, like scan and BIST, can cover a vast but not complete spectrum of all the possible defects. It appears that the divide-and-conquer approach founded on structural techniques may not be enough to reach every single element or to effectively stimulate the faulty behaviors that may show up during the lifetime of the device. Burn-In is widely used to reduce Infant Mortality, accelerating the evolution of weak points into defects via externally or internally induced stress.In this work, we focus on internal stress and present a generation strategy intended to automatically produce functional stress procedures for the Burn-In phase that exacerbate possible weak points which are likely to escape activation by structural tests, such that they more easily outbreak during the successive final test procedures. The proposed generation strategy primarily addresses the interconnections to embedded memories, which look challenging to stress by structural methods, including Logic and Memory BIST, and critical due to the integration of different technologies (i.e., logic gates and memory layout). In the considered test case, the proposed approach increases the average toggle activity by orders of magnitude with respect to Memory BIST. Furthermore, it provides a uniform distributed toggling activity.Results collected on an automotive SoC show how the stress provided by functional programs compares with the stress level provided by structural test methods measured in terms of toggling activity. The SpeedUp produced by the proposed procedure is 3.14X wrt to the MBIST executing the March C-algorithm.

Testing and validation check a hardware device or a software application against the desired design requirements. They are a vital part of all steps of system engineering and typically account for a significant percentage of the overall development cost. This paper presents a novel technique to provide a quick preliminary evaluation of functional test procedures of various natures, ranging from Software-Based Self-Test to Burn-In Functional Stress and System-level tests. We define a new metric called “connectivity”, which is fast to compute and can be used to guide functional program development. The method does not require logic or fault simulations, and it is based on the analysis of the execution trace generated by the functional program. To summarize our process, we first obtain the trace directly from the chip, running the software through a debugger. Then, we create a graph representation of the program data flow. Finally, we analyze the graph to identify instructions that negatively impact the final coverage. We perform experiments on an automotive device manufactured by STMicroelectronics, and we demonstrate the effectiveness of the approach in terms of computation time and beneficial effects on the fault coverage.