Boolean Satisfiability (SAT), an NP-complete problem central to EDA and AI, has motivated hardware acceleration to overcome its exponential complexity. Early approaches focused on speeding up incomplete solvers, but their inherent algorithmic limitations made them unsuitable for correctness-critical tasks. Consequently, the focus shifted to hardware accelerators for complete solvers based on the DPLL/CDCL framework, which concentrated on accelerating the primary bottleneck: the Boolean Constraint Propagation (BCP) operation. However, performance is ultimately dominated by branching heuristics. Existing designs either omit heuristics, suffering large penalties, or offload them to CPUs, incurring prohibitive overhead. This work presents Heuristic-in-Macro (HiM), the first fully autonomous SAT accelerator integrating both an efficient BCP engine and a hardware-embedded MOMs branching heuristic in a single macro, eliminating CPU dependence. A high-throughput parallel processing architecture replaces traditional serialized clause scans with a tiled multi-macro execution, achieving 8.78× acceleration. At the circuit level, physical efficiency is enhanced through a compact 16T unit cell that merges logic and storage, thereby reducing area and energy. Proposed HiM-based solver achieves 100% SAT/UNSAT solvability, 172.1× speedup in algorithmic performance compared to designs without heuristics. When matched against a CPU-offloaded hybrid system, HiM is 305.6× faster and 1.99×106× more energy-efficient. Compared to the widely used MiniSAT software solver, HiM delivers 26.7× speedup and 3.09×106× efficiency, while reducing time- and energy-to-solution by up to 94% and 83% versus state-of-the-art ASIC accelerators.

Advances in semiconductor scaling and integration have increased design complexity, concentrating valuable IP in single chips. Reverse engineering using high-resolution microscopy techniques, such as scanning electron microscopy (SEM) and transmission electron microscopy (TEM), enables detailed circuit analysis and extraction of layout-level information. At the same time, reliance on external foundries increases the risks of design information leakage. To address these challenges, we propose a Fast Post-Manufacturing Programmable Camouflaged (FP2C) Logic Family, which consists of physically identical logic structures that are activated by applying a post-programming code (PC) after fabrication. The proposed FP2C logic-embedded Flip-Flop (FP2C logic-eFF) was implemented using a 28nm CMOS process, achieving a 67% reduction in cell area compared to prior Post-Manufacturing Programmed Threshold Voltage Defined (PMP-TVD) logic cells on the same technology node. Furthermore, this paper presents a systematic design methodology that integrates FP2C logic-eFF into an EDA tool-based digital circuit design flow. This enables FP2C logic to move beyond prior camouflaged logic that was limited to full-custom arithmetic unit implementations, and extend to complex digital IPs. To validate its feasibility, an AES module was designed and its functionality was verified through SPICE simulation, thereby demonstrating the applicability of FP2C logic to complex digital modules.

Growing demand to deepen understanding of the human brain has accelerated efforts to identify the structure of biological neural networks from neuronal activities. This paper presents a fully digital, tile-able neural array integrated circuit(IC) that, to our knowledge, is the first hardware platform for network reconstruction—inferring synaptic connectivity directly from spike-train data generated by a biological (ground-truth) network. Designed with the overarching goal of emulation of biological networks, the architecture employs repeatable digital neuron-module tiles to ensure the scalability, flexibility and verifiability. Two chip-level run-time interfaces are integrated: a writable spike-forcing path for injecting biological spike pulses into selected IC neurons for synchronized co-firing, and a dedicated monitoring path for streaming spike events, synaptic weights, and membrane potentials. Scalability is further enabled by single-timer Δt capture and a piecewise-linear STDP Δw generator shared per neuron, avoiding complex LUTs/multipliers while preserving biological plausibility. The platform is realized in silicon and tested with an FPGA-based setup. Using only spike activity, the system reconstructs synaptic connectivity with high fidelity across diverse ground-truth networks ranging from simple 2-layer topologies to biologically derived C.elegans head network, as well as networks with bimodal and trimodal weight distributions. Accuracy was comprehensively quantified from multiple perspectives for both connectivity and spike-train similarity, confirming faithful replication. These results demonstrate that the proposed platform can recover the synaptic structure from spikes alone and provide a practical tool for predicting network learning responses under varied stimuli, advancing biological neural network research and real-time neuromorphic experimentation.

This paper presents a 6.78-MHz inductive wireless power transfer (WPT) system designed for implantable medical devices (IMDs). To meet the stringent IMD limits on form factor, power conversion efficiency (PCE), and regulation, the proposed system adopts a resonant current-mode (RCM) method. A compact RX coil, under spatial constraints, necessitates the adoption of the RCM method, which provides a voltage conversion ratio greater than unity, enabling efficient transfer of the energy stored in the LC tank to the output. To achieve high regulation performance, a deficit-energy-quantifying (DEQ) resonant regulating rectifier (3R) is introduced. The DEQ-3R operates by quantifying the energy deficit to reach the target output voltage and comparing it with the LC-tank energy. Comparison result detects the transition timing from the resonance phase to the charging phase with a delay-compensated comparator (DCC) adaptive to the LC-tank energy level. The proposed DEQ-3R is implemented in a 180-nm CMOS process, occupying 1.04 mm2 active area. Experiment results using an 80-nH RX coil demonstrate regulated 2.5-V operation over a coupling-coefficient range of 0.1-0.16 and a load power range of 5-45 mW. The prototype achieves a peak PCE of 81.28%, reflecting a 6.08% improvement over a counterpart without the DEQ, while reducing the VOUT ripple from 432mVPP to 168mVPP with a 20-nF output capacitor.

A novel Resistive random access memory (ReRAM)-based Compute-in-memory (CIM) macro is proposed to overcome the limited accuracy and throughput of a conventional ReRAM-based CIM macro that results from to the low R-Ratio and large variation of ReRAM. The proposed structure consists of 1T2R1C bit-cells and 4-kb ReRAM-based nvCIM architecture with ternary weight and ternary input. Ternary multiplication is implemented with voltage division between paired ReRAM devices within a bit-cell to make the output voltage variation tolerant and less sensitive to low R-ratios. An accumulation operation is realized with capacitive coupling so that linearity can be guaranteed for a large number of operands, allowing accurate and fast multiply-and-accumulate (MAC) operations. For comprehensive validation of the proposed CIM macro, the Verilog-A models for ReRAM devices with an adjustable R-ratio and adjustable variations are adopted to perform simulation on various R-ratio and variation conditions. With the peripheral circuits designed in 180-nm CMOS technology, the proposed CIM macro is confirmed to have high variation tolerance, high throughput, and less sensitivity to a low R-ratio, resulting in a high ternary DNN accuracy of 99.07% (0.01% drop) for the MNIST and 83.79% (0.38% drop) for the CIFAR-10 data sets with an R-ratio as low as 38 and 20%/40% low/high resistance variation.