Packet schedulers are essential for managing packet transmission order in high-speed networks, where scheduling metadata must be processed at line rate under bursty traffic conditions. In such systems, packet scheduling and traffic management operate on compact packet descriptors rather than on full packets. FIFO-based schedulers are attractive for their simplicity and throughput, but implementations that statically partition descriptor memory across queues must provision for worst-case occupancy, leading to inefficient memory utilization. This paper presents MetaFlex, a scalable architecture for efficient implementation of calendar-queue–based packet scheduling using shared descriptor memory. MetaFlex dynamically allocates descriptor storage to scheduling queues on demand, allowing memory to be effectively shared across a large number of rank bins while maintaining constant-time enqueue and dequeue operations. Rather than introducing a new scheduling algorithm, MetaFlex focuses on the architectural realization of shared-memory descriptor queues that scale to large queue counts with predictable timing and modest hardware cost. We evaluate MetaFlex using NS2 simulations of weighted fair scheduling and a hardware prototype implemented in VHDL on an AMD/Xilinx Alveo U250 FPGA board. Simulation results show that MetaFlex achieves comparable or lower packet loss than fixed-memory calendar queues under identical descriptor-memory budgets, while using substantially less descriptor storage under typical traffic conditions. The FPGA prototype operates at 322 MHz, sustains 100 Gb/s line rate for packets larger than 370 bytes, and uses less than 1% of logic resources and less than 5% of on-chip memory, demonstrating the practicality of MetaFlex for high-speed hardware datapaths.