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Carlos Bilbao

dblp:323/9565 · DBLP profile ↗
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4ranked-venue papers
2as first author
4since 2021 · last 2024
0000-0002-4750-5124ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Parallel and multicore computing · 54% Memory systems · 40% Performance modeling and evaluation · 6%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%

Topics — the 8 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Operating systems › resource management › process management › CPU scheduling
NUMA-aware scheduling
0.712023
Divide&Content: A Fair OS-Level Resource Manager for Contention Balancing on NUMA Multicores · IEEE Trans. Parallel Distributed Syst. 2023
Operating systems
resource management
0.712023
Divide&Content: A Fair OS-Level Resource Manager for Contention Balancing on NUMA Multicores · IEEE Trans. Parallel Distributed Syst. 2023
Memory systems › cache management
cache partitioning
0.712023
Divide&Content: A Fair OS-Level Resource Manager for Contention Balancing on NUMA Multicores · IEEE Trans. Parallel Distributed Syst. 2023
Memory systems › cache management › cache partitioning
last-level cache partitioning
0.712023
Divide&Content: A Fair OS-Level Resource Manager for Contention Balancing on NUMA Multicores · IEEE Trans. Parallel Distributed Syst. 2023
Parallel and multicore computing › task allocation
thread placement
0.712023
Divide&Content: A Fair OS-Level Resource Manager for Contention Balancing on NUMA Multicores · IEEE Trans. Parallel Distributed Syst. 2023
Parallel and multicore computing › parallel programming runtimes
OpenMP runtime
0.512021
An OpenMP Runtime for Transparent Work Sharing across Cache-Incoherent Heterogeneous Nodes · ACM Trans. Comput. Syst. 2021
Parallel and multicore computing
parallel programming models and runtimes
0.512021
An OpenMP Runtime for Transparent Work Sharing across Cache-Incoherent Heterogeneous Nodes · ACM Trans. Comput. Syst. 2021
Parallel and multicore computing › parallel scheduling
loop scheduling
0.112021
An OpenMP Runtime for Transparent Work Sharing across Cache-Incoherent Heterogeneous Nodes · ACM Trans. Comput. Syst. 2021

Methods — techniques the papers use, named apart from their topics

measurement · 1.3kernel implementation · 1.3runtime scheduling · 0.5performance profiling · 0.5
YearPublicationVenuePosition
2024 Exploiting Elasticity via OS-Runtime Cooperation to Improve CPU Utilization in Multicore Systems
abstract
The chip multicore processor (CMP) architecture has become the predominant design choice for contemporary general-purpose systems across multiple sectors of commercial technology. Thanks to technological progress, CMP systems can now feature hundreds of cores. While multithreaded applications may potentially benefit from the increasing core counts, leveraging all available cores is not always feasible due to limited Thread-Level Parallelism (TLP), load imbalance among threads, and other scalability bottlenecks. Colocating multiple applications on the same node is becoming a popular practice to maximize processor utilization. In HPC, malleability -the ability to dynamically alter the number of active threads within the same application-, is also being exploited at the runtime-system level to better deal with scenarios exhibiting time-varying scalability. In the cloud, application colocation is leveraged along with different forms of coarse-grained elasticity to cater to the varying resource demands. This work introduces an operating system (OS) level elastic mechanism designed to efficiently leverage idle CPU periods in workloads consisting of unmodified applications, many of which do not rely on a runtime system to function. This mechanism constitutes a form of fine-grained vertical elasticity that leverages cooperation between the runtime sys-tem and the OS to maximize CPU utilization. To this end, it opportunistically increases the active thread count of mal-leable applications during idle periods. We implemented our proposed OS extensions in the Linux kernel, and augmented the GNU's OpenMP runtime to show a proof of concept of the required OS-runtime interaction. By using diverse multi- threaded programs, we demonstrate the ability of the proposed OS support to substantially improve the system throughput.
Javier Rubio, Carlos Bilbao, Juan Carlos Saez, Manuel Prieto 0001
PDP2
2023 Flexible system software scheduling for asymmetric multicore systems with PMCSched: A case for Intel Alder Lake
abstract
Summary Asymmetric multicore processors (AMPs) couple high‐performance big cores and power‐efficient small ones, all exposing a shared instruction set architecture to software, but with different microarchitectural features. The energy efficiency benefits of AMPs, together with the general‐purpose nature of the various cores, have led hardware manufacturers to build commercial AMP‐based products, first for the mobile and embedded domains, and more recently, for the desktop market segment, as with the Intel Alder Lake processor family. This trend indicates that AMPs may become a solid and more energy efficient replacement for symmetric multicores in a wide range of application domains. Previous research has demonstrated that the system software can substantially improve scheduling—critical to get the most out of heterogeneous cores—by leveraging hardware facilities that are directly managed by the OS, such as performance monitoring counters, or the recently introduced Intel Thread Director technology. Unfortunately, the OS‐level support enabling access to these hardware facilities may often take a long time to be adopted in operating systems, or may come in forms that make its utilization challenging from specific levels of the system software stack, especially in production systems. To fill this gap, we propose PMCSched, an open‐source framework enabling rapid development and evaluation of custom scheduling‐related support in the Linux kernel. PMCSched greatly simplifies the design and implementation of a wide range of scheduling policies for multicore systems that operate at different system software layers without requiring to patch the kernel. To demonstrate the potential of our framework, we conduct a set of experimental case studies on asymmetry‐aware scheduling for Intel Alder Lake processors.
Carlos Bilbao, Juan Carlos Saez, Manuel Prieto 0001
Concurr. Comput. Pract. Exp.1
2023 Divide&Content: A Fair OS-Level Resource Manager for Contention Balancing on NUMA Multicores
abstract
Chip multicore processors (CMPs) constitute the cherry-picked architecture for high-performance servers employed in supercomputers and cloud datacenters. In the last few years, Non-Uniform Memory Access (NUMA) multicore systems have become the dominant choice in these domains. Regardless of the technology advances enabling to pack an increasing number of cores and bigger caches on the same chip, contention for shared resources still represents an important challenge for the system software. Cores in CMPs typically share multiple resources, such as the last-level cache (LLC) or a DRAM controller. The competition for the usage of these resources leads to uneven performance degradation across co-running applications. Previous research has demonstrated that contention effects on CMPs can be mitigated via smart partitioning of the LLC or by distributing threads across groups of cores so as to even out the degree of competition on multiple LLCs or memory nodes. However, most existing resource-management strategies fail to effectively combine both contention-mitigating techniques, thus providing suboptimal results on NUMA multicores. In this paper, we analyze how to best combine these techniques to improve system-wide fairness, and, based on the conclusions of our analysis, propose a fair OS-level NUMA-aware resource manager that leverages dynamic contention-aware thread-to-socket mappings and cache-partitioning. We implemented our resource manager in the Linux kernel and assessed its effectiveness on a real dual-socket system featuring Intel Skylake processors. Our results show that it reduces unfairness by more than 17% on average compared to Linux and a state-of-the-art NUMA-aware resource manager.
Carlos Bilbao, Juan Carlos Saez, Manuel Prieto 0001
IEEE Trans. Parallel Distributed Syst.1
2021 An OpenMP Runtime for Transparent Work Sharing across Cache-Incoherent Heterogeneous Nodes
abstract
In this work, we present libHetMP , an OpenMP runtime for automatically and transparently distributing parallel computation across heterogeneous nodes. libHetMP targets platforms comprising CPUs with different instruction set architectures (ISA) coupled by a high-speed memory interconnect, where cross-ISA binary incompatibility and non-coherent caches require application data be marshaled to be shared across CPUs. Because of this, work distribution decisions must take into account both relative compute performance of asymmetric CPUs and communication overheads. libHetMP drives workload distribution decisions without programmer intervention by measuring performance characteristics during cross-node execution. A novel HetProbe loop iteration scheduler decides if cross-node execution is beneficial and either distributes work according to the relative performance of CPUs when it is or places all work on the set of homogeneous CPUs providing the best performance when it is not. We evaluate libHetMP using compute kernels from several OpenMP benchmark suites and show a geometric mean 41% speedup in execution time across asymmetric CPUs. Because some workloads may showcase irregular behavior among iterations, we extend libHetMP with a second scheduler called HetProbe-I. The evaluation of HetProbe-I shows it can further improve speedup for irregular computation, in some cases up to a 24%, by triggering periodic distribution decisions.
Robert Lyerly, Carlos Bilbao, Changwoo Min, Christopher J. Rossbach, Binoy Ravindran
ACM Trans. Comput. Syst.2