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John X. Przybysz

dblp:324/3691 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design
0.011989
Josephson shift registers · Proc. IEEE 1989
Integrated circuit design › digital circuit design › sequential circuit design
shift register
0.011989
Josephson shift registers · Proc. IEEE 1989
YearPublicationVenuePosition
1989 Josephson shift registers
abstract
A review of Josephson shift-register circuits that have been designed, fabricated, or tested is presented with emphasis on work in the 1980s. Operating speed is most important, since it often limits system performance. Older designs used square-wave clocks, but most modern designs use offset sine waves, with either two or three phases. Operating margins and gate bias uniformity are key concerns. The fastest measured Josephson shift register operated at 2.3 GHz, which compares well with a GaAs shift register that consumes 250 times more power. The difficulties of high-speed testing have prevented many Josephson shift registers from being operated at their highest speeds. Computer simulations suggest that 30-GHz operation is possible with current Nb/Al/sub 2/O/sub 3//Nb technology. Junctions with critical current densities near 10 kA/cm/sup 2/ would make 100-GHz shift registers feasible.>
John X. Przybysz
Proc. IEEE1