As system designers are transitioning to the usage of pre-existing software architectural elements to reduce time-to-market and costs, they face challenges in safety-critical applications. Pre-existing software may have been implemented without following any safety and/or quality standard, and its documentation may be incomplete or unclear. As recommended by part 6 of the functional safety standard ISO 26262 (product development at the software level), stringent rules and guidelines must be followed during the implementation of a new software. The qualification of a pre-existing software according to ISO 26262 may hence be very time consuming and expensive if not addressed in a structured way. This work presentsSTPA for Pre-existing Software(STPA-PES), a new software hazardous behavior analysis approach designed to identify criticalities or abnormal conditions in complex pre-existing software to be mitigated with adequate safety measures. The major challenge in such a process consists in the definition of a model that correctly represents the system under analysis when the architectural design of pre-existing software is not available. As a relevant example, the proposed approach is finally applied to dynamic memory allocator (DynMA) in Linux kernel to show how STPA-PES is able to derive safety requirements of this software architectural element.

The complexity of vehicle applications and the need of reducing the number of processing units are giving great audience to system virtualization. Virtualized architectures with diverse Automotive Safety Integrity Level (ASIL) in the same multicore hardware, known as Mixed Criticality Systems (MCSs), offer flexibility but are extremely challenging in terms of timing validation and resources partitioning. At the same time, RISC- V technologies are becoming central in automotive thanks to open source licensing and customizable solutions. However, most of these architectures cannot sustain MCSs for the absence of features that can be performed only through hardware extensions. In this paper we define details and show a preliminary design and synthesis of a Programmable PMU (PPMU). In virtual systems an extension reporting hardware performance is essential to absolve timing analysis and shared resources balancing purposes. Moreover, in the paper we present a table containing major Hardware Events (HEs) we are interested in, and that can be monitored. The HEs are classified by the role they have in a MCS: Functional Safety (FuSa) analysis or Performance analysis. The synthesis of the PPMU highlighted that the device introduces a limited hardware overhead, e.g. in the worst case the unit uses less than 3 % of available programmable logic of a xczu9eg FPGA device.