As semiconductor manufacturing advances from the 3-nm process toward the sub-nanometer regime and transitions from FinFETs to gate-all-around field-effect transistors (GAAFETs), the resulting complexity and manufacturing challenges continue to increase. In this context, 3D chiplet-based approaches have emerged as key enablers to address these limitations while exploiting the expanded design space. Specifically, chiplets help address the lower yields typically associated with large monolithic designs. This paradigm enables the modular design of heterogeneous systems consisting of multiple chiplets (e.g., CPUs, GPUs, memory) fabricated using different technology nodes and processes. Consequently, it offers a capable and cost-effective strategy for designing heterogeneous systems.This paper introduces the Horizon Europe Twinning project COIN-3D (Collaborative Innovation in 3D VLSI Reliability), which aims to strengthen research excellence in 2.5D/3D VLSI systems reliability through collaboration between leading European institutions. More specifically, our primary scientific goal is the provision of novel open-source Electronic Design Automation (EDA) tools for reliability assessment of 3D systems, integrating advanced algorithms for physical- and system-level reliability analysis.

As semiconductor manufacturing technologies progress beyond the current 3nm, the demand for more compact and powerful VLSI circuits obliges on-chip power grid networks to become denser, resulting in a substantial increase in current densities. Consequently, Electromigration (EM) has emerged as a critical reliability concern since it can lead to voids on the metal wires and, consequently, large IR drops. In this paper, we present an EM/IR-aware wire sizing methodology based on the Particle Swarm Optimization (PSO) algorithm. Our methodology can be effectively applied to contemporary power grid networks to achieve the targeted lifetimes of the chip, and simultaneously resize the wires for area reduction. The advantage is that the proposed approach is able to deal with high-dimensional search spaces, which is imperative in our problem. Experimental results using the large-scale industrial IBM power grid benchmarks indicate that our new approach can increase the lifespan of the power grid up to 6.47 × while effectively reducing the area up to 65%.

Efficient sound density simulation for room acoustic models is a challenging problem, due to the need for the solution of large-scale systems of equations that require unreasonably long computational times. However, in many cases, the measurement of sound density is not required to be computed at every point of the entire room but only at certain spots. This makes the room acoustic problem amenable to Model Order Reduction (MOR) techniques. Moment-Matching (MM) techniques are well established and can be directly applied in the resulting sound diffusion equation. In this paper, we propose a computationally efficient MM algorithm based on extended Krylov subspace method, that can generate very compact models in order to efficiently simulate them across many time-steps. Experimental results demonstrate a speedup up to 1016× with relative error less than 0.5%.

Traditional approaches to analyzing electromigration (EM) in on-chip interconnects are largely driven by semi-empirical models. However, such methods are inexact for the typical multisegment lines that are found in modern integrated circuits. This paper overviews recent advances in analyzing EM in on-chip interconnect structures based on physics-based models that use partial differential equations, with appropriate boundary conditions, to capture the impact of electron-wind and back-stress forces within an interconnect, across multiple wire segments. Methods for both steady-state and transient analysis are presented, highlighting approaches that can solve these problems with a computation time that is linear in the number of wire segments in the interconnect.

As integrated circuit technologies move below 10 nm, Electromigration (EM) has become an issue of great concern for the longterm reliability due to the stricter performance, thermal and power requirements. The problem of EM becomes even more pronounced in power grids due to the large unidirectional currents flowing in these structures. The attention for EM analysis during the past years has been drawn to accurate physics-based models describing the interplay between the electron wind force and the back stress force, in a single Partial Differential Equation (PDE) involving wire stress. In this paper, we present a fast semi-analytical approach for the solution of the stress PDE at discrete spatial points in multi-segment lines of power grids, which allows the analytical calculation of EM stress independently at any time in these lines. Our method exploits the specific form of the discrete stress coefficient matrix whose eigenvalues and eigenvectors are known beforehand. Thus, a closed-form equation can be constructed with almost linear time complexity without the need of time discretization. This closed-form equation can be subsequently used at any given time in transient stress analysis. Our experimental results, using the industrial IBM power grid benchmarks, demonstrate that our method has excellent accuracy compared to the industrial tool COMSOL while being orders of magnitude times faster.