The instruction set architecture of vector processors operates on vectors stored in the vector register file which needs to handle several concurrent accesses by functional units with multiple ports. When the vector processor is running with high utilization, access conflicts become a major source of performance degradation. With a software model of a vector processor, we take a deep dive into the runtime impact of conflicts and their characteristics, and on ways to manage them, i.e., avoidance, resolution, and mitigation. For conflict avoidance, we study the existing approaches of banking with different static bank layouts and propose a dynamic bank layout to overcome their shortcomings. Our approach assigns newly written registers a temporarily unique starting bank. For conflict resolution, we compare different arbitration algorithms and optimize round-robin arbitration for mixed-width arithmetics by prioritizing wide operands. For conflict mitigation, operand queues of varying depths are studied. Our inventions are likely to increase the area efficiency of vector processors, either because they allow to use shallower operand queues while keeping the same performance, or reduce the area even further by using less banks, albeit at a performance impairment of 10% or less. The insights of the study can further be applied to other shared memory systems.

Embedded systems usually integrate multiple Pro-cessing Elements (PEs) on a single chip. Various PEs are con-nected to the same Tightly Coupled Memory (TCM) to increase the area and energy efficiency. However, memory sharing comes at the cost of conflicts resulting in performance degradation. To counteract this issue, Access Interval Prediction (AIP) has been introduced in the literature to predict the interval between two memory accesses. State-of-the-art AIP units are based on predictors proposed for branch prediction, such as TAgged GEometric (TAGE). This work shows for the first time that several types of neural networks are suitable for AIP as well. By treating AIP as a classification problem, we can continue to decrease the error rate compared to the TAGE predictor. For example, Vision Transformer (ViT) networks reduce the average error rate by over one-third to 2.1 percent. Through our investigation, we demonstrate that offline training alone is sufficient since the memory access traces contain the same repetitive patterns independent from the input parameters of the program run.

Flexible and scalable solutions will be needed for future communications processing systems. RISC-V processors enhanced with vector processing capabilities as specified by the soon-to-be ratified RISC-V vector extension (RVV) pose an interesting base for such systems. Vector processors provide an efficient means of exploiting data-level parallelism, which is heavily present in communications kernels. Furthermore, RVV code is by its design agnostic from the underlying hardware platform which enables scalability. On the exemplary basis of a generalized frequency division multiplexing (GFDM) implementation on a RVV processor, we investigate its baseband processing capabilities and guide through RVV's key features and peculiarities. Our vectorization achieves a speedup of up to 60 times compared to the scalar base case and a throughput of 784 symbols per second. The utilization of 77 % is slightly below more specialized solutions. Nevertheless, this work serves as a baseline for further investigations on flexible and scalable RISC-V vector communications processors.