Lightweight anonymity protocols provide a well-balanced anonymity and performance by encrypting and decrypting only packet headers under the active and local adversary threat model. Among them, PHI and dPHI are promising in universally providing relationship anonymity. However, when overlaid onto IP, they are susceptible to the router skipping attack, where honest routers are skipped by malicious routers. Although this attack poses a significant threat to anonymity, its prevention is challenging due to the lack of path integrity in these protocols. To address this limitation, this paper integrates path validation into dPHI. This integration is non-trivial, as anonymity and path validation are inherently contradictory requirements. This paper designs and implements pPHI, a novel protocol, and analyzes pPHI in terms of security and performance.

Although secure channels are an essential building block of data plane protocols, their realization on programmable switches remains a significant challenge. Typical approaches offload the computation of authenticated encryption to external devices, compromising either speed or flexibility. Similarly, recent efforts to implement existing constructions of authenticated encryption on the switches face performance limitations due to the numerous recirculations required. This paper presents a novel construction and implementation of authenticated encryption on the switches. It incorporates two instances of Chaskey, a PRF with high compatibility with the switches, to achieve both confid-entiality and integrity with fewer recirculations, integrated using the EtM approach. Multi-block data are handled in CCM mode, implemented through a block rotation mechanism. Furthermore, a divide-and-conquer method realized through packet multi-furcation and rendezvous further reduces recirculations. The construction is verified for security, and its implementation on a Tofino 2 switch exhibits substantial performance improvements.

Programmable switches offer a promising platform for fast and flexible in-network computing. However, a standard mechanism, packet recirculation, degrades throughput due to bandwidth consumption caused by the loopback of not only packet headers but also cumbersome payloads. This paper proposes P4QRS, a mechanism that reduces payload recirculation by retaining payloads within the switch. Specifically, P4QRS bifurcates packets into headers and payloads, which undergo the computation process through pipelines and the buffering process leveraging the switch’s queue behavior, respectively. The headers and payloads then rendezvous for reassembly into complete packets to be sent out. To validate its effectiveness, we evaluated P4QRS through both an analytical model and implementation on state-of-the-art hardware programmable switches. Our results demonstrate that P4QRS operates stably and significantly accelerates complex in-switch computations. Moreover, we address packet reordering, which is a fundamental concern arising because P4QRS performs payload buffering on a per-packet basis rather than per-flow. After identifying the mechanism for developing packet reordering in three stages, we design, implement, and evaluate mitigation strategies targeting each stage. These strategies effectively suppress packet reordering in both flow-aware and flow-unaware cases.

Programmable switches are promising platforms for fast and flexible in-network computation; however, a standard mechanism, packet recirculation, degrades throughput due to bandwidth consumption caused by the loopback of not only packet headers but also cumbersome payloads. This paper proposes$\mathrm{P}^{4} \text{QRS}$, a mechanism for retaining payloads within the switch, reducing payload recirculations. Specifically,$\mathrm{P}^{4}$QRS bifurcates packets into headers and payloads, which undergo the computation process through pipelines and the buffering process leveraging the switch's queue behavior, respectively; they then rendezvous for reassembly into complete packets to be sent out. To validate its effectiveness, we evaluated$\mathrm{P}^{4}$QRS using an analytical model and implementation on state-of-the-art hardware programmable switches. Our evaluation shows that$\mathrm{P}^{4}$QRS operates stably and intrinsically boosts complex in-switch computations.

Consumer privacy leakage from data names poses a serious threat to Content-Centric Networking (CCN) networks. Obfuscating names is a promising countermeasure, and anonymizers with deterministic encryption schemes have been proposed to provide data privacy while enabling CCN features, such as in-network caching. Existing studies assume a weak threat model in which anonymizers are honest, and their obfuscation schemes are not resilient against privacy attacks such as name guessing attacks. This paper designs a name obfuscation framework based on the realistic assumption that anonymizers are semi-honest. The framework strengthens data privacy using multiple keys and separates obfuscation for prefixes and suffixes, and is implemented on a P4 switch to provide Tbps forwarding speed.

The paper presents a Tbps-class anonymity router that supports both an anonymity protocol and IP by leveraging a programmable switch. The key design issue is to place both the compute-intensive header decryption function for anonymity protocol forwarding and the memory-intensive IP forwarding function on the processing pipes of a switch with satisfying its hardware requirements. A prototype router on a programmable switch achieves Tbps-scale forwarding.