High-bandwidth memory (HBM) has enabled substantial advancements in bandwidth-intensive applications, including large-scale artificial intelligence models. HBM is typically integrated with other systems-on-chip (SoCs) through a silicon interposer, and the primary bottleneck in aggressively scaling the bandwidth in next-generation HBM systems stems from significant crosstalk caused by closely spaced, high-density parallel interconnects in the interposer. While crosstalk avoidance code (CAC) has emerged as a promising solution, prior CAC schemes suffer from low bit efficiency and considerable hardware overhead. This article proposes an efficient CAC scheme, WITCH, which employs a novel weighted coding strategy. Unlike prior approaches that consider all channels identically, WITCH assigns different weights to channels based on their relative positions in the array, enabling more bit-efficient crosstalk suppression. We also present WITCH with additional shielding (WITCH-AS), an extension of WITCH that incorporates additional shielding to further reduce crosstalk levels. Our coding schemes achieve high bit efficiency, up to 17.3% higher than state-of-the-art techniques while providing an identical level of crosstalk reduction. Simulation results using an industry-proven channel model demonstrate that WITCH and WITCH-AS improve eye height by 10.1%–49.4% and 17.1%–51.1%, respectively. Furthermore, we propose an area- and energy-efficient hardware implementation that can be integrated into real-world HBM systems. The design reduces area and critical path delay by 31.0% and 28.2%, respectively, compared with conventional designs. Finally, we propose a compatible simultaneous switching output (SSO) noise mitigation technique that can be seamlessly integrated into WITCH to further enhance signal integrity under high-speed, high-density operating conditions.

High bandwidth memory (HBM) has enabled a breakthrough in bandwidth-bound applications, including large-scale artificial intelligence models. HBM is typically connected to other SoCs through a silicon interposer. However, the increasing density of the parallel interconnect wires incurs significant amount of crosstalk, hindering bandwidth improvement in the next-generation HBMs. While Crosstalk Avoidance Code (CAC) has emerged as a solution to mitigate crosstalk, prior CAC schemes suffer from low bit efficiency and significant hardware overhead. This paper proposes an efficient CAC scheme, WITCH. It employs a new coding system, weighted coding, which gives a different emphasis to each channel according to its relative position in the channel array. This enables crosstalk reduction with higher bit efficiency than prior CACs treating all channels in the array equally. The extended version of WITCH, WITCH-AS, is also proposed with additional shielding for further crosstalk reduction. Our coding system shows high bit efficiency of 91.2--91.7% and 84.3--84.6% for WITCH and WITCH-AS, which is up to 20.8% higher than the state-of-the-art schemes while preserving the same crosstalk level reduction. We have shown through simulations using an industry-proven channel model that WITCH and WITCH-AS improve the eye heights by 10.1--49.4% and 17.1--51.1% respectively. In addition, this paper presents an efficient hardware implementation of our coding schemes which shows 28.2% lower critical path delay and 31.0% smaller area than conventional implementation, proving itself a practical solution for HBMs.

This paper describes a variation-robust transceiver with four-tap feed-forward equalization (FFE) and real-time calibration techniques. The design adopts the common-mode balanced and robust FFE (CMBB-FFE), which improves the previous current-mode coefficient-error-robust FFE (B-FFE) to achieve the consistent common-mode level across data patterns and support voltage mode operation. The real-time receiver calibration method adjusts sampling threshold voltages and clock phases in the middle of normal link operation, to enhance the sampling margin under dynamic drifting conditions. The transceiver test chip is fabricated in a 28-nm CMOS process. It occupies 0.419 mm$^{\mathbf {2}}$, achieving 20 Gb/s with 9.82-pJ /bit energy efficiency and 33.3% wider horizontal eye-opening by adopting the CMBB-FFE and real-time calibration techniques.

This article presents an automatic layout generation framework in advanced CMOS technologies. The framework extends the template-and-grid-based layout generation methodology to produce optimal layouts more efficiently. Layout templates and grids are dynamically created and adjusted during the generation phase to provide more reusability and flexibility. Virtual instances are used to encapsulate the dynamically generated layout structures. Internal node probes embedded in the dynamic templates capture parasitic effects precisely. The framework also implements various post-processing functions to handle process-specific tasks while maintaining the overall process portability of procedural layout generators. The post-processing functions include cut/dummy pattern generation and multiple-patterning adjustment. The generator description coverage is enhanced with circular grid indexing/slicing and conditional conversion operators. The layout generation framework is applied to generate various DRC/LVS clean layouts automatically in advanced CMOS technologies, achieving 0.66–249.35 transistors-per-line (the ratio of the generated transistor count to the source lines of code) generation efficiencies.