This paper presents the process of generating the layout of the 8-bit Successive Approximation Register Analog to Digital Converter (SAR ADC). By utilizing LAYGO2 [1], a Python framework that allows for detailed and flexible specification of custom layout generation processes, code-based generators for the component blocks of a SAR ADC were developed according to their specific operational characteristics and requirements. As a result, 85.5% of the SAR ADC was automatically generated. The SAR ADC test chip was fabricated in a 14-nm CMOS FinFET process and achieved an SNDR of 41.67 dB at 500 MS/s, consuming 2.07 mW from 0.9 V supply, and occupying an area of 4,131 um2.

This paper presents a high-speed single-ended 4-level pulse amplitude modulation (PAM-4) transceiver for next-generation memory interfaces, achieving a data rate of 32Gb/s. The proposed asymmetrically terminated PAM-4 driver is optimized for pseudo open drain (POD) channel configurations and improves signal-to-noise ratio (SNR) with a larger output swing. The dynamic logic-based high-speed 4-to-1 serializer enhances the transmitter output’s jitter characteristic by avoiding high-frequency components in the selection signals. The 4-tap feed-forward equalizer (FFE) with two operation modes and one sliding tap flexibly compensates for inter-symbol interference (ISI) of the channel. In the receiver frontend, a continuous-time linear equalizer (CTLE), which utilizes a trans-admittance stage (TAS) and a trans-impedance amplifier (TIA) with an inductive load, provides high-frequency boosting and robust single-to-differential conversion performance through the design techniques of current source gain-boosting and capacitive compensation. The low kickback noise comparators mitigate clock feedthrough and noise coupling during multi-phase PAM-4 sampling and embed the 1-tap PAM-4 decision feedback equalizer (DFE) operation by directly feeding back the previous sampling phase’s outputs. The transceiver prototype fabricated in 28-nm CMOS technology occupies 0.126 mm2. At 32 Gb/s, a bit error rate of under$10^{-12}$was achieved with a 6.25% eye margin and an energy efficiency of 3.37 pJ/bit while equalizing the 6.87-dB channel loss at 8 GHz.

This article presents an automatic layout generation framework in advanced CMOS technologies. The framework extends the template-and-grid-based layout generation methodology to produce optimal layouts more efficiently. Layout templates and grids are dynamically created and adjusted during the generation phase to provide more reusability and flexibility. Virtual instances are used to encapsulate the dynamically generated layout structures. Internal node probes embedded in the dynamic templates capture parasitic effects precisely. The framework also implements various post-processing functions to handle process-specific tasks while maintaining the overall process portability of procedural layout generators. The post-processing functions include cut/dummy pattern generation and multiple-patterning adjustment. The generator description coverage is enhanced with circular grid indexing/slicing and conditional conversion operators. The layout generation framework is applied to generate various DRC/LVS clean layouts automatically in advanced CMOS technologies, achieving 0.66–249.35 transistors-per-line (the ratio of the generated transistor count to the source lines of code) generation efficiencies.