Generating diverse VLSI layout patterns is essential for various downstream tasks in design for manufacturing, as design rules continually evolve during the development of new technology nodes. However, existing training-based methods for layout pattern generation rely on large datasets. In practical scenarios, especially when developing a new technology node, obtaining such extensive layout data is challenging. Consequently, training models with large datasets becomes impractical, limiting the scalability and adaptability of prior approaches. To this end, we propose PatternPaint, a diffusion-based framework capable of generating legal patterns with limited design-rule-compliant training samples. PatternPaint simplifies complex layout pattern generation into a series of inpainting processes with a template-based denoising scheme. Furthermore, we perform few-shot finetuning on a pretrained image foundation model with only 20 design-rule-compliant samples. Experimental results show that using a sub-3nm technology node (Intel 18A), our model is the only one that can generate legal patterns in complex 2D metal interconnect design rule settings among all previous works and achieves a high diversity score. Additionally, our few-shot finetuning can boost the legality rate by 1.87 X compared to the original pretrained model. As a result, we demonstrate a production-ready approach for layout pattern generation in developing new technology nodes.

A step-based tutoring system is being developed to improve student learning in elementary linear circuit analysis courses. The approach is based on the known importance of viewing worked examples or solutions in alternation with problem-solving exercises of the same type, to avoid excessive cognitive loads when learning a new skill. The system can generate an unlimited supply of circuit problems (with randomly varying topologies) similar to those in textbooks and corresponding fully explained solutions for both DC, AC, and transient analysis. Solution methods and topics include voltage and current division, node and mesh analysis, superposition, Thévenin and Norton equivalents, Bode plots, and Laplace analysis. Special pedagogical devices are used to reduce extraneous cognitive load when using the system, such as color-coding nodes and equation terms. Qualitative conceptual topics such as series and parallel connections are given special emphasis. The system has been used to date by over 2860 students in 71 class sections at 10 different colleges and universities of widely varying types, with generally very favorable student ratings. Evaluation has included a series of randomized, controlled trials in both laboratory and classroom settings to rigorously assess student learning gains as well as the impact of the materials on student motivation and preferences. Learning improvements of 0.72 std. deviations are found in comparison to a publisher-based homework system for node analysis, and 0.97 std. deviations for identification of elements in series and parallel compared to paper exercises.