Gallium Nitride (GaN) platforms are reshaping the efficiency, frequency, and form factor of power electronics integrated circuits. However, the absence of p-channel transistors of GaN technologies makes traditional electrostatic discharge (ESD) protection for integrated circuits (ICs) ineffective. This letter proposes a protection network for input/output pins that leverages the unique conduction properties of enhancement-mode GaN transistors in the third quadrant of their current-voltage (I-V) plane. Experimental measurements confirm the viability of the proposed solution as a library element of the process design kit.

This paper presents the design and experimental measurement of a fully integrated gate driver fabricated together with a 200-V GaN power switch in a GaN-on-SOI technology. The driver exploits 20-V low-voltage enhancement-mode HEMTs (E-HEMTs), Metal-Insulator-Metal (MIM) bootstrap capacitors and two-dimensional electron gas (2DEG) resistors. To overcome the inherent lack of p-channel devices in the GaN technology, the design employs the bootstrapping approach which allows for full turn-on of the 200-V power GaN switch while minimizing static power consumption. Furthermore, the relatively high breakdown voltage (20 V) of the low-power E-HEMTs allows them to withstand the high voltages generated during bootstrapping. Static power consumption is further reduced by minimizing the number of ratioed logic inverters and implementing an anti-cross-conduction network to eliminate cross-conduction switching losses. The design also leverages the third quadrant of the HEMTs’$I_{\mathrm{DS}}-V_{\mathrm{DS}}$characteristic to emulate the diode behavior, potentially reducing external component requirements. Measured performance reveals an average gate driver current consumption ranging from$370 \mu \mathrm{~A}$at -40°C to$150 \mu \mathrm{~A}$at 150°C. Additionally, the rise and fall times when driving the power switch with 365-m$\Omega$on-resistance are respectively 6.5 ns and 3.5 ns at room temperature.

Modern high-performance electronics is pushing Si technology to its limits. Gallium Nitride (GaN) emerges as a promising alternative due to its superior properties in high-frequency and high-power applications. To fully utilize the fast-switching ability of the GaN technology, monolithic integration is a key. A monolithically integrated GaN power IC (Integrated Circuit) reduces the inductive parasitic enabling a fast efficient switching operation. However, GaN basic building blocks, particularly operational amplifiers (Op-Amps), face severe challenges due to the limitations of the GaN technology. This paper presents the first three-stage Op-Amp for high-performance feedback circuits realized in the IMEC’s 200-V GaN-IC technology on a GaN-on-SOI (Silicon on Insulator) substrate. The design utilizes a cascade of three differential stages resistively loaded to achieve a nearly 60-dB DC gain and 25-MHz gain-bandwidth and implements a novel dual single-Miller frequency compensation technique to provide closed-loop stability. The Op-Amp offers a Slew Rate exceeding 70 V/μs with 1% settling time of about 120 ns at room temperature. The correct circuit functionality from −40 °C to 150 °C was demonstrated through simulations and experimental test.

This paper presents for the first time a fully integrated galvanic isolation interface in a GaN technology. It is based on planar micro-antennas and chip-to-chip communication with an on-off keying-modulated RF carrier. This approach can achieve high isolation rating and high common-mode transient immunity by properly setting the distance between chips. The interface provides the isolation channel for a main driver/power switch and the one for the control feedback of the dc-dc converter providing the isolated power supply. Driver and power control channels adopt an RF carrier of 2 GHz and 1.2 GHz, which are modulated by a pulse width modulated signal of 2 MHz and 0.5 MHz, respectively. The interface includes a continuously operating offset compensation approach, which overcomes not only the strong variations due to the large process tolerances of the GaN technology, but also offset drifts due to temperature variations. An accurate pulse width modulated signal with a large duty cycle variation in both channels was achieved. The isolation interface adopts a 6-V power supply, which delivers a quiescent current of 6.3 mA and 7.5 mA to the driver and power control channels, respectively, assuming a signal with a duty cycle of 50%.

This paper presents a frequency compensation scheme of a full GaN operational amplifier for smart power applications. The amplifier is based on a previous topology originally developed for nMOS technology and here adapted for a modern GaN process. The solution is able to drive a capacitive load as high as 1 nF and a suitable design strategy has been developed. The operational amplifier exhibits a very high nominal DC gain of about 135 dB, a unity-gain bandwidth of about 560 kHz with 60° phase margin, a slew rate of about 0.83 V/$\mu$s and a nominal quiescent current consumption of 200 $\mu$A from a 6-V supply.