We address the problem of minimizing the area of circuits mapped to a technology library, with or without delay constraints. While traditional methods optimize first a technology-independent representation and then perform technology mapping to a library, this paper explores the potential for further optimizations through technology-dependent algorithms. We propose an optimization engine for mapped circuits that relies on a database of mapped sub-networks for efficient resynthesis. Experimental results on the EPFL benchmarks after area-oriented optimization and mapping show that the proposed method leads to average area improvements of 5.47% without degrading the delay.

This paper presents a novel resynthesis engine for minimizing the dynamic power of digital circuits. Traditional logic synthesis methods primarily focus on zero-delay toggles—logic state changes occurring between the start and end of a clock cycle. In contrast, our engine targets both zero-delay toggles and glitches, unintended transitions within a clock cycle caused by path imbalances. Glitches significantly contribute to power consumption in arithmetic circuits, making their minimization a critical challenge in electronic design. The proposed method uses a database of Pareto-optimal netlists to replace sub-networks in the target circuit with power-efficient alternatives. These replacements are guided by a simulation-driven cost function that evaluates workload-independent switching activity and penalizes gates with high fan-out. We call our approach Lazy Man’s Resynthesis because it builds on an algorithm named Lazy Man’s Synthesis, extending it from technology-independent delay optimization to post-mapping power optimization. Applied to the ISCAS and EPFL benchmarks, our method reduces glitching activity by 4.72% and dynamic power by 9.44%, achieving a 7.61% improvement over the state-of-the-art.

This paper addresses the challenge of reducing the number of nodes in Look-Up Table (LUT) networks with two significant applications. First, Field-Programmable Gate Arrays (FPGAs) can be modelled as networks of LUTs, and minimizing the node count is imperative to meet resource constraints. Second, in area-oriented design space exploration for standard-cell designs, collapsing a circuit into a LUT network, restructuring it, and later remapping to the original representation helps escape local minima. Thus, the development of algorithms for optimizing and restructuring LUT networks holds considerable promise for area-oriented optimization. Substitution (also called resubstitution) is a powerful logic minimization method that can identify non-local logic dependencies and exploit them for logic minimization. State-of-the-art substitution algorithms for LUT networks rely heavily on SAT solving, limiting the number of optimization attempts and the size of the substitution sub-networks to one node mishchenko2011scalable. Conversely, our method relies on circuit simulation to increase the number of substitution candidates and enables substitutions with more than one node. The experimental results show that the proposed method identifies optimization opportunities overlooked by other methods, improving 11 out of 23 best-known results in the EPFL synthesis competition and yielding a 3.46% area reduction compared to the state-of-the-art.

Logic synthesis is an ensemble of algorithms that optimizes digital circuit representations and maps them to a chosen technology. Minimizing the number of gates is essential to reduce area occupation and power consumption. As the problem is intractable, heuristic logic transformations are used. In particular, resubstitution attempts to express the function of a node using other nodes already present in the network. State-of-the-art resubstitution engines can only identify new implementations with support of up to three inputs or being simply decomposable. This work aims at extending resubstitution to non-decomposable functions with more than three inputs and it outperforms previous methods. We apply our method on highly optimized designs from the ISCAS and EPFL benchmarks, achieving additional average improvements of 18.50% and 8.36%.

Logic Synthesis From Partial Specifications (LSFPS) is the problem of finding the hardware implementation of a Boolean function from a partial knowledge of its care set. The elements missing from the specifications are named don’t knows. The exact solution of LSFPS is the minimum size circuit of the corresponding problem in which the don’t knows set is void. Hence, in addition to the traditional objective of size minimization, the goal is to maximize the test accuracy, i.e., the accuracy of the circuit when evaluated over a subset of the don’t knows. This problem is relevant because efficient solutions can lead to hardware friendly machine learning models, not relying on black-box approaches. Indeed, LSFPS maps directly to the problem of the automatic generation of optimized topologies for Binarized Neural Networks. Furthermore, combining the exact solution with modern logic synthesis techniques would unlock unprecedented optimization capabilities. Previous works proved the effectiveness of approximate logic synthesis (ALS) for designing circuits with high test accuracy. Nonetheless, these methods sacrifice accuracy on the specifications, which banishes them from the legitimate candidates for LSFPS. In this paper, we propose accuracy recovery, a procedure to map an approximate version of the circuit to a new one that satisfies the exact functionality of the specifications. The proposed approach relies on an extension of a disjoint support decomposition algorithm. Relative experiments on the IWLS2020 benchmarks show that, on average, the addition of the designed decomposition to a synthesis flow reduces by 17.38% the number of gates and by 12.02% the depth. The usage of accuracy recovery, based on such a decomposition, yields a 95.73% accuracy in the binary MNIST problem, beating the state-of-the-art in ALS of 92.76%.